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    Generation of delay values for a simulation model of circuit elements in a clock network
    1.
    发明授权
    Generation of delay values for a simulation model of circuit elements in a clock network 有权

    公开(公告)号：US09639640B1

    公开(公告)日：2017-05-02

    申请号：US14693506

    申请日：2015-04-22

    Applicant: Xilinx, Inc.

    Inventor： Nagaraj Savithri ,  Robert M. Ondris ,  Chiao K. Hwang

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/5054 ,  G06F2217/62 ,  G06F2217/84

    Abstract: An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

    Transceiver for providing a clock signal
    2.
    发明授权
    Transceiver for providing a clock signal 有权
    收发器用于提供时钟信号

    公开(公告)号：US09148192B1

    公开(公告)日：2015-09-29

    申请号：US13962468

    申请日：2013-08-08

    Applicant: Xilinx, Inc.

    Inventor： Alan C. Wong ,  Christopher J. Borrelli ,  Loren Jones ,  Seu Wah Low ,  Parag Upadhyaya ,  Robert M. Ondris ,  Sarosh I. Azad

    IPC: H04B1/40

    CPC classification number: H04L25/14

    Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

    Abstract translation: 公开了一种与用于提供时钟信号的收发机或发射机的发射机侧有关的装置。 在该装置中，第一信号源是提供第一周期信号。 第二信号源是提供第二周期信号。 第一多路复用器被耦合以接收第一周期性信号和第二周期信号，以将其选定的一个作为第一选择输出。 相位插值器耦合到第一多路复用器以接收第一选择的输出。 相位插值器包括第二多路复用器。 第二多路复用器被耦合以接收第一选择输出和第一选择输出的相位插值版本，以将其选定的一个输出作为第二选择输出。 分频器耦合到第二多路复用器以接收第二选择的输出以提供时钟信号。

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