知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.014 seconds)

    Implementing an application specified as a data flow graph in an array of data processing engines
    2.
    发明授权
    Implementing an application specified as a data flow graph in an array of data processing engines 有权

    公开(公告)号：US11301295B1

    公开(公告)日：2022-04-12

    申请号：US16421434

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Shail Aditya Gupta ,  Rishi Surendran

    IPC: G06F9/46 ,  G06F9/50 ,  G06F16/901 ,  G06F13/28

    Abstract: Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.

    Routing in a compilation flow for a heterogeneous multi-core architecture
    3.
    发明授权
    Routing in a compilation flow for a heterogeneous multi-core architecture 有权

    公开(公告)号：US11138019B1

    公开(公告)日：2021-10-05

    申请号：US16420935

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Akella Sastry ,  Henri Fraisse ,  Rishi Surendran ,  Abnikant Singh

    IPC: G06F9/445 ,  G06F13/40 ,  G06F16/901 ,  G06F13/28

    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

    FLOW CONVERGENCE DURING HARDWARE-SOFTWARE DESIGN FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
    4.
    发明申请
    FLOW CONVERGENCE DURING HARDWARE-SOFTWARE DESIGN FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES 审中-公开

    公开(公告)号：US20200371787A1

    公开(公告)日：2020-11-26

    申请号：US16421439

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Shail Aditya Gupta ,  Rishi Surendran

    IPC: G06F9/30 ,  G06F9/46 ,  G06F9/50 ,  G06F8/41

    Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

    Packet identification (ID) assignment for routing network
    5.
    发明授权
    Packet identification (ID) assignment for routing network 有权

    公开(公告)号：US11615052B1

    公开(公告)日：2023-03-28

    申请号：US16420946

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Rishi Surendran ,  Akella Sastry ,  Abnikant Singh

    IPC: G06F15/78 ,  G06F16/901 ,  G06F30/20 ,  H04L49/109 ,  H04L49/25

    Abstract: Some examples described herein relate to packet identification (ID) assignment for a routing network in a programmable integrated circuit (IC). In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to construct an interference graph based on routes of logical nets through switches in a routing network, and assign identifications to the routes comprising performing vertex coloring of vertices of the interference graph. The interference graph includes the vertices and interference edges. Each vertex represents one of the logical nets having a route. Each interference edge connects two vertices that represent corresponding two logical nets that have routes that share at least one port of a switch. The identifications correspond to values assigned to the vertices by the vertex coloring.

    Flow convergence during hardware-software design for heterogeneous and programmable devices
    6.
    发明授权
    Flow convergence during hardware-software design for heterogeneous and programmable devices 有权

    公开(公告)号：US10891132B2

    公开(公告)日：2021-01-12

    申请号：US16421439

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Shail Aditya Gupta ,  Rishi Surendran

    IPC: G06F9/30 ,  G06F8/41 ,  G06F9/50 ,  G06F9/46

    Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

Patent Agency Ranking