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    HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
    1.
    发明申请
    HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES 有权

    公开(公告)号：US20220035607A1

    公开(公告)日：2022-02-03

    申请号：US17500509

    申请日：2021-10-13

    Applicant: Xilinx, Inc.

    Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

    IPC: G06F8/41 ,  H03K19/17724

    Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

    Dataflow graph programming environment for a heterogenous processing system
    2.
    发明授权
    Dataflow graph programming environment for a heterogenous processing system 有权

    公开(公告)号：US11204745B2

    公开(公告)日：2021-12-21

    申请号：US16420831

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Shail Aditya Gupta ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Akella Sastry

    IPC: G06F9/44 ,  G06F8/41 ,  G06F16/901 ,  G06F9/54 ,  G06F15/78

    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

    Hardware and software cosynthesis performance estimation
    5.
    发明授权
    Hardware and software cosynthesis performance estimation 有权
    硬件和软件合成性能估算

    公开(公告)号：US09147024B1

    公开(公告)日：2015-09-29

    申请号：US14535258

    申请日：2014-11-06

    Applicant: Xilinx, Inc.

    Inventor： Vinod K. Kathail ,  Hua Sun ,  Sundararajarao Mohan ,  L. James Hwang ,  Yogesh L. Chobe

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5045

    Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

    Abstract translation: 硬件和软件协同合成性能估计包括对于以高级编程语言指定的设计并具有处理器可执行分区和为硬件加速选择的分区，估计所选分区的硬件加速器实现的硬件延迟，调度所选择的 分区，使用硬件延迟生成硬件分区延迟信息，并使用处理器编译设计版本的设计。 设计的仪器化和编译版本执行生成软件延迟信息。 通过将硬件分区延迟信息与软件延迟信息相结合来确定设计的设计性能。

    Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
    7.
    发明授权
    Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices 有权

    公开(公告)号：US11645053B2

    公开(公告)日：2023-05-09

    申请号：US17500509

    申请日：2021-10-13

    Applicant: Xilinx, Inc.

    Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

    IPC: G06F8/41 ,  H03K19/17724

    CPC classification number: G06F8/41 ,  G06F8/447 ,  H03K19/17724

    Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

    Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
    8.
    发明授权
    Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices 有权

    公开(公告)号：US11188312B2

    公开(公告)日：2021-11-30

    申请号：US16421444

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

    IPC: G06F8/41 ,  H03K19/17724

    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

    HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
    10.
    发明申请
    HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES 审中-公开

    公开(公告)号：US20200371759A1

    公开(公告)日：2020-11-26

    申请号：US16421444

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddarth Rele

    IPC: G06F8/41 ,  H03K19/177

    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

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