公开(公告)号：US10971474B1

公开(公告)日：2021-04-06

申请号：US16289975

申请日：2019-03-01

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.

公开(公告)号：US20190131265A1

公开(公告)日：2019-05-02

申请号：US15798748

申请日：2017-10-31

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49872 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03001 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/11001 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81002 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/0561 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

公开(公告)号：US20180358280A1

公开(公告)日：2018-12-13

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US11302674B2

公开(公告)日：2022-04-12

申请号：US16880811

申请日：2020-05-21

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  William E. Allaire ,  Hong Shi ,  Kerry M. Pierce

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

公开(公告)号：US11217550B2

公开(公告)日：2022-01-04

申请号：US16044363

申请日：2018-07-24

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L23/00 ,  H01L21/3065 ,  H01L21/78

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

公开(公告)号：US20200303341A1

公开(公告)日：2020-09-24

申请号：US16361617

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

公开(公告)号：US10770430B1

公开(公告)日：2020-09-08

申请号：US16361617

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

公开(公告)号：US20200161229A1

公开(公告)日：2020-05-21

申请号：US16194213

申请日：2018-11-16

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.

公开(公告)号：US20200035635A1

公开(公告)日：2020-01-30

申请号：US16044363

申请日：2018-07-24

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L23/00 ,  H01L21/3065 ,  H01L21/78

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

公开(公告)号：US10319606B1

公开(公告)日：2019-06-11

申请号：US15813008

申请日：2017-11-14

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H01L23/14

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.