公开(公告)号：US08922242B1

公开(公告)日：2014-12-30

申请号：US14185587

申请日：2014-02-20

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan

IPC: H03K19/007 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17768

Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.

Abstract translation: 公开了用于备份可编程IC的一组可编程逻辑电路中包括的双稳态电路的值的方法和电路。 可编程逻辑电路被配置为实现具有基于存储在多个配置存储器单元的使用部分中的数据值的功能的逻辑电路。 可编程IC包括配置为备份和恢复双稳电路的值的备用控制电路。 响应于第一信号，由双稳电路存储的第一数据值被检索并存储在多个配置存储器单元中的第一个未被用于实现逻辑电路的配置存储器单元中。 响应于第二信号，第一数据值从多个配置存储器单元中的第一个被检索并存储在双稳态电路中。

公开(公告)号：US09436562B1

公开(公告)日：2016-09-06

申请号：US14171488

申请日：2014-02-03

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Chen W. Tseng

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/1625 ,  G06F11/1004

Abstract: An apparatus relating generally to an error detection system is disclosed. The apparatus includes a first data bus and a second data bus. A first circuit is coupled for communication via the first data bus. A plurality of storage elements are coupled to the first data bus and the second data bus. A second circuit is coupled for communication via the second data bus. The error detection system is coupled to the first data bus and the second data bus. The error detection system is coupled to compare first data on the first data bus with corresponding second data on the second data bus. The error detection system is configured to generate an error signal responsive to mismatch between the first data and the second data.

Abstract translation: 公开了一般涉及错误检测系统的装置。 该装置包括第一数据总线和第二数据总线。 第一电路被耦合用于经由第一数据总线进行通信。 多个存储元件耦合到第一数据总线和第二数据总线。 第二电路被耦合用于经由第二数据总线进行通信。 误差检测系统耦合到第一数据总线和第二数据总线。 错误检测系统被耦合以将第一数据总线上的第一数据与第二数据总线上的对应的第二数据进行比较。 错误检测系统被配置为响应于第一数据和第二数据之间的不匹配而产生误差信号。

公开(公告)号：US09208043B1

公开(公告)日：2015-12-08

申请号：US13842140

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Restu I. Ismail ,  Robert Le

IPC: G06F11/00 ,  G06F11/263

CPC classification number: G06F11/263 ,  G01R31/31816 ,  G01R31/318342

Abstract: A method, non-transitory computer readable medium, and apparatus for performing fault injection and verification on an integrated circuit are disclosed. For example, the method generates a mask file for one or more modules of a hierarchical design, wherein the mask file identifies one or more essential bits, receives a selection of one of the one or more modules as a selected module for the fault injection and the verification to be applied, performs the fault injection on at least one essential bit of the selected module based upon the mask file for the selected module, and performs the verification on the selected module.

Abstract translation: 公开了一种在集成电路上执行故障注入和验证的方法，非暂时计算机可读介质和装置。 例如，该方法为分层设计的一个或多个模块生成掩模文件，其中掩模文件识别一个或多个必要位，接收作为用于故障注入的所选模块的一个或多个模块之一的选择， 要应用的验证，基于所选模块的掩模文件对所选模块的至少一个基本位执行故障注入，并对所选模块执行验证。

公开(公告)号：US08635581B1

公开(公告)日：2014-01-21

申请号：US13842502

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan ,  Matthew H. Klein ,  Restu I. Ismail

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G06F11/263 ,  G06F2217/14

Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract translation: 公开了一种用于执行单事件不正常检测和校正的方法，非暂时性计算机可读介质和装置。 例如，该方法包括：由处理器设置用于集成电路的设计的多行中的每一行的至少一个起始地址，由处理器设置用于多个集合电路中的每一个的至少一个结束地址 并且由处理器并行执行单个事件镦锻检测和校正扫描，从多个行中的每个行的至少一个起始地址到多个行中的每一个的至少一个结束地址 行。