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公开(公告)号：US20210098582A1
公开(公告)日：2021-04-01
申请号：US16097838
申请日：2018-09-14
Inventor： Yuan Yan , Lisheng Li , Dewei Song
IPC: H01L29/417 , H01L29/66 , H01L29/786 , H01L27/12
Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.
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公开(公告)号：US11114468B2
公开(公告)日：2021-09-07
申请号：US16475137
申请日：2019-03-25
Inventor： Xin Zhang , Lisheng Li , Peng He
IPC: H01L27/12 , H01L29/423
Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.
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Patent Agency Ranking
公开(公告)号：US10957713B2
公开(公告)日：2021-03-23
申请号：US16097277
申请日：2018-09-13
Inventor： Lisheng Li , Guanghui Liu
IPC: H01L27/12
Abstract: The present invention teaches a LTPS TFT substrate and its manufacturing method. The manufacturing method, after forming vias using the photoresist layer on the ILD layer and the gate insulation layer above the source/drain contact regions, and before peeling the photoresist layer, forms conductive layers in the vias by depositing conductive material in the vias. The source/drain electrodes contact the conductive layers in the vias and therefore are conducted to the source/drain contact regions, thereby effectively resolving the problem of contact impedance being too high between the source/drain electrodes and the source/drain contact regions from the existing re-etch LDD technique. Then, through the re-etch LDD technique, the present invention is able to omit a mask process without sacrificing product characteristics. In addition, the vias and the photoresist layer have undercut structure, preventing the deposited conductive material from affecting the photoresist layer's peeling and guaranteeing the photoresist layer's peeling efficiency.
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公开(公告)号：US20210091124A1
公开(公告)日：2021-03-25
申请号：US16309446
申请日：2018-09-18
Inventor： Lisheng Li , Guanghui Liu
Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.
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5.发明授权公开(公告)号：US11101387B2
公开(公告)日：2021-08-24
申请号：US16344018
申请日：2018-11-19
Inventor： Lisheng Li , Peng He , Yuan Yan
IPC: H01L29/78 , H01L29/786 , H01L21/02 , H01L29/10 , H01L29/66
Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.
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公开(公告)号：US10964790B1
公开(公告)日：2021-03-30
申请号：US16097838
申请日：2018-09-14
Inventor： Yuan Yan , Lisheng Li , Dewei Song
IPC: H01L29/417 , H01L29/66 , H01L29/786 , H01L27/12 , H01L29/45 , H01L21/311
Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.
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公开(公告)号：US10957721B1
公开(公告)日：2021-03-23
申请号：US16309446
申请日：2018-09-18
Inventor： Lisheng Li , Guanghui Liu
Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.
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