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    METHOD FOR GATE STACK FORMATION AND ETCHING
    1.
    发明申请
    METHOD FOR GATE STACK FORMATION AND ETCHING 审中-公开

    公开(公告)号：US20200273992A1

    公开(公告)日：2020-08-27

    申请号：US16782680

    申请日：2020-02-05

    Applicant: Tokyo Electron Limited

    Inventor： Sergey Voronin ,  Christopher Catano ,  Sang Cheol Han ,  Shyam Sridhar ,  Yusuke Yoshida ,  Christopher Talone ,  Alok Ranjan

    IPC: H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3065

    Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

    METHOD TO ACHIEVE A SIDEWALL ETCH
    2.
    发明申请
    METHOD TO ACHIEVE A SIDEWALL ETCH 审中-公开

    公开(公告)号：US20190259623A1

    公开(公告)日：2019-08-22

    申请号：US16277760

    申请日：2019-02-15

    Applicant: Tokyo Electron Limited

    Inventor： Shyam Sridhar ,  Nayoung Bae ,  Sergey Voronin ,  Alok Ranjan

    IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/3213

    Abstract: Sidewall etching of substrate features may be achieved by employing an etch stop layer formed over the features. The etch stop layer is thinner on sidewalls of the features as compared to the bottom of the features. The lateral etching of the features is achieved by use of an over etch which breaks through the etch stop layer on the sidewalls of the features but does not break through the etch stop layer formed at the bottom of the features. The use of the etch stop layer allows for lateral etching while preventing unwanted vertical etching. The lateral etching may be desirable for use in a number of structures, including but not limited to 3D structures. The lateral etching may also be used to provide vertical sidewalls by reducing the sidewall taper angle.

    Topographic selective deposition
    3.
    发明授权
    Topographic selective deposition 有权

    公开(公告)号：US12224160B2

    公开(公告)日：2025-02-11

    申请号：US18322362

    申请日：2023-05-23

    Applicant: Tokyo Electron Limited

    Inventor： Shyam Sridhar ,  Peter Lowell George Ventzek ,  Alok Ranjan

    IPC: H01J37/32

    Abstract: A method of processing a substrate that includes: flowing a gas including a fluorocarbon to a plasma processing chamber; sustaining a plasma generated from the gas; depositing a carbonaceous layer over the substrate by exposing the substrate to the plasma, the substrate having a recess having an aspect ratio between 10:1 and 100:1, the depositing including a pulsed plasma process including: during a first time duration, setting a source power (SP) at a first SP level and a bias power (BP) at a first BP level, where the plasma includes fluorocarbon ions polymerizing on a bottom surface to form the carbonaceous layer, and during a second time duration, setting the SP at a second SP level higher than the first SP level and the BP at a second BP level lower than the first BP level, where the plasma includes fluorine radicals trimming the carbonaceous layer.

    Topographic Selective Deposition
    4.
    发明申请
    Topographic Selective Deposition 有权

    公开(公告)号：US20240395507A1

    公开(公告)日：2024-11-28

    申请号：US18322362

    申请日：2023-05-23

    Applicant: Tokyo Electron Limited

    Inventor： Shyam Sridhar ,  Peter Lowell George Ventzek ,  Alok Ranjan

    IPC: H01J37/32

    Abstract: A method of processing a substrate that includes: flowing a gas including a fluorocarbon to a plasma processing chamber; sustaining a plasma generated from the gas; depositing a carbonaceous layer over the substrate by exposing the substrate to the plasma, the substrate having a recess having an aspect ratio between 10:1 and 100:1, the depositing including a pulsed plasma process including: during a first time duration, setting a source power (SP) at a first SP level and a bias power (BP) at a first BP level, where the plasma includes fluorocarbon ions polymerizing on a bottom surface to form the carbonaceous layer, and during a second time duration, setting the SP at a second SP level higher than the first SP level and the BP at a second BP level lower than the first BP level, where the plasma includes fluorine radicals trimming the carbonaceous layer.

    Plasma processing methods using multiphase multifrequency bias pulses
    6.
    发明授权
    Plasma processing methods using multiphase multifrequency bias pulses 有权

    公开(公告)号：US12217935B2

    公开(公告)日：2025-02-04

    申请号：US17807076

    申请日：2022-06-15

    Applicant: Tokyo Electron Limited

    Inventor： Ya-Ming Chen ,  Shyam Sridhar ,  Peter Lowell George Ventzek ,  Alok Ranjan

    IPC: H01J37/32

    Abstract: A plasma processing method includes generating a plasma within a processing chamber using source power to ignite a glow phase of the plasma, generating low-energy ions at a substrate supported by a substrate holder in the processing chamber from the plasma using lower-frequency radio frequency bias power applied during the glow phase, and generating high-energy ions at the substrate using higher-frequency radio frequency bias power applied during an afterglow phase of the plasma. The frequency of the higher-frequency radio frequency bias power is greater than the frequency of the lower-frequency radio frequency bias power.

    Balanced RF Resonant Antenna System
    7.
    发明公开
    Balanced RF Resonant Antenna System 审中-公开

    公开(公告)号：US20240363310A1

    公开(公告)日：2024-10-31

    申请号：US18308877

    申请日：2023-04-28

    Applicant: Tokyo Electron Limited

    Inventor： Qiang Wang ,  Michael Hummel ,  Peter Lowell George Ventzek ,  Shyam Sridhar ,  Mitsunori Ohata

    IPC: H01J37/32 ,  H01Q5/10

    CPC classification number: H01J37/32183 ,  H01J37/32091 ,  H01Q5/10

    Abstract: According to an embodiment, a plasma processing system includes a plasma chamber, an RF source, a matching circuit, a balun, and a resonating antenna. The resonating antenna includes a first and a second spiral resonant antenna (SRA), each having an electrical length corresponding to a quarter of a wavelength of a frequency of a forward RF wave generated by the RF source. The first end of the first SRA is coupled to a first balanced terminal of the balun and the second end of the first SRA is open circuit. The first end of the second SRA is coupled to a second balanced terminal of the balun and the second end of the second SRA is open circuit. The first and the second SRA are arranged in a symmetrically nested configuration having a same center point.

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