公开(公告)号：US11581314B2

公开(公告)日：2023-02-14

申请号：US16723939

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US10224245B2

公开(公告)日：2019-03-05

申请号：US15076762

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

公开(公告)号：US10515856B2

公开(公告)日：2019-12-24

申请号：US16271522

申请日：2019-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pin Linus Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

公开(公告)号：US12094880B2

公开(公告)日：2024-09-17

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.