公开(公告)号：US11996298B2

公开(公告)日：2024-05-28

申请号：US17890980

申请日：2022-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/088

CPC classification number: H01L21/477 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/0886

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

公开(公告)号：US20230120117A1

公开(公告)日：2023-04-20

申请号：US17705004

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/324

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

公开(公告)号：US20240387628A1

公开(公告)日：2024-11-21

申请号：US18786532

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

公开(公告)号：US12087771B2

公开(公告)日：2024-09-10

申请号：US17476136

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.

公开(公告)号：US20240297239A1

公开(公告)日：2024-09-05

申请号：US18177911

申请日：2023-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Chun-Fu Lu ,  Hsiang-Pi Chang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, forming a superlattice structure including first and second nanostructured layers on the fin base, forming a polysilicon structure on the superlattice structure, epitaxially growing a S/D region on the fin base and adjacent to the first nanostructured layer, forming an oxygen-rich outer gate spacer including a first dielectric material with a first non-stoichiometric composition on a sidewall of the polysilicon structure, forming an oxygen-rich inner gate spacer including a second dielectric material with a second non-stoichiometric composition on a sidewall of the second nanostructured layer, and replacing the polysilicon structure with a gate structure.