-
公开(公告)号：US20230367234A1
公开(公告)日：2023-11-16
申请号：US18360618
申请日：2023-07-27
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
IPC分类号： G03F9/00
CPC分类号： G03F9/7026 , G03F7/2004
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
公开(公告)号：US20230384691A1
公开(公告)日：2023-11-30
申请号：US18361879
申请日：2023-07-30
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705
摘要： A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.
-
公开(公告)号：US10418245B2
公开(公告)日：2019-09-17
申请号：US15664222
申请日：2017-07-31
发明人： Chih-Jie Lee , Joy Cheng
IPC分类号： H01L21/033 , G06F17/50 , H01L21/027 , H01L21/02 , G03F1/36
摘要： A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.
-
公开(公告)号：US12085867B2
公开(公告)日：2024-09-10
申请号：US18360618
申请日：2023-07-27
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
CPC分类号： G03F9/7026 , G03F7/2004 , G03F7/2041
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
公开(公告)号：US11789370B2
公开(公告)日：2023-10-17
申请号：US17665757
申请日：2022-02-07
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
IPC分类号： G06F30/392 , G03F7/00 , G03F1/36
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705
摘要： A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.
-
公开(公告)号：US20190035630A1
公开(公告)日：2019-01-31
申请号：US15664222
申请日：2017-07-31
发明人： Chih-Jie Lee , Joy Cheng
IPC分类号： H01L21/033 , G06F17/50 , H01L21/027 , H01L21/02 , G03F1/36
CPC分类号： H01L21/0338 , G03F1/36 , G03F7/0002 , G06F17/5009 , G06F17/5081 , G06F2217/12 , H01L21/02118 , H01L21/02356 , H01L21/0271 , H01L21/0274 , H01L21/0337
摘要： A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.
-
公开(公告)号：US11467509B2
公开(公告)日：2022-10-11
申请号：US17301215
申请日：2021-03-29
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
公开(公告)号：US20200301289A1
公开(公告)日：2020-09-24
申请号：US16895547
申请日：2020-06-08
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
摘要： A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.
-
公开(公告)号：US20190146355A1
公开(公告)日：2019-05-16
申请号：US16057277
申请日：2018-08-07
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
IPC分类号： G03F7/20
摘要： Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.
-
公开(公告)号：US11782352B2
公开(公告)日：2023-10-10
申请号：US17815155
申请日：2022-07-26
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
CPC分类号： G03F9/7026 , G03F7/2004 , G03F7/2041
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.017 秒)
