公开(公告)号：US20250054562A1

公开(公告)日：2025-02-13

申请号：US18514258

申请日：2023-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Wei LIN ,  Meng-Sheng CHANG

IPC: G11C29/52 ,  G11C7/08 ,  G11C29/02

Abstract: An integrated circuit includes a first set of memory cells configured to store a first set of data, a second set of memory cells configured to store a second set of data, a first set of input output (IO) circuits coupled to the first set of memory cells, a second set of IO circuits coupled to the second set of memory cells, a first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder/decoder circuit configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of ECC bits and the second number of ECC bits.

公开(公告)号：US20240268107A1

公开(公告)日：2024-08-08

申请号：US18165296

申请日：2023-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Shao-Tung PENG ,  Chung-I HUANG

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: An integrated circuit includes a first active region, a second active region, a first fuse and a dummy fuse. The first active region extends in a first direction, and is on a first level. The second active region extends in the first direction, is on the first level, and is separated from the first active region in a second direction different from the first direction. The first fuse extends in the first direction, is on a second level, overlaps the first active region and is electrically coupled to the first active region. The dummy fuse extends in the first direction, is on the second level, and is separated from the first fuse in the second direction. The dummy fuse overlaps the second active region, and is not electrically coupled to the second active region.

公开(公告)号：US20240049459A1

公开(公告)日：2024-02-08

申请号：US18448022

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: H10B20/20 ,  H01L23/525

CPC classification number: H10B20/20 ,  H01L23/5252

Abstract: A metal fuse structure may be provided. The metal fuse structure may comprise a first fuse element and a second fuse element. The second fuse element may be adjacent to the first fuse element for a length L. The second fuse element may be spaced apart from first fuse element by a width W.

公开(公告)号：US20230215804A1

公开(公告)日：2023-07-06

申请号：US18182760

申请日：2023-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Po-Hsiang HUANG ,  An-Jiao FU ,  Chih-Hao CHEN

IPC: H01L23/525 ,  G06F30/39

CPC classification number: H01L23/5256 ,  G06F30/39 ,  G06F2119/18

Abstract: A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

公开(公告)号：US20220384339A1

公开(公告)日：2022-12-01

申请号：US17885321

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

IPC: H01L23/525 ,  H01L27/112

Abstract: A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

公开(公告)号：US20210082812A1

公开(公告)日：2021-03-18

申请号：US16573761

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Po-Hsiang HUANG ,  An-Jiao FU ,  Chih-Hao CHEN

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

公开(公告)号：US20200058660A1

公开(公告)日：2020-02-20

申请号：US16533359

申请日：2019-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  G11C17/18 ,  G06F17/50 ,  G11C17/16

Abstract: A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

公开(公告)号：US20250006282A1

公开(公告)日：2025-01-02

申请号：US18503386

申请日：2023-11-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: G11C17/16 ,  G11C17/18

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a first transistor, the second transistor, a first circuit, a second circuit and a third transistor. The second transistor is electrically connected to the first transistor, wherein gates of the first transistor and the second transistor are electrically connected to a word line. The first circuit is electrically connected between a drain of the first transistor and a first bit line. The second circuit is electrically connected between a drain of the second transistor and a second bit line. The third transistor is electrically connected between the drain of the first transistor and the drain of the second transistor.

公开(公告)号：US20230354591A1

公开(公告)日：2023-11-02

申请号：US18346700

申请日：2023-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Chien-Ying CHEN ,  Chia-En HUANG ,  Yih WANG

IPC: H10B20/20 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B20/20 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/528

Abstract: A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.

公开(公告)号：US20220285375A1

公开(公告)日：2022-09-08

申请号：US17193594

申请日：2021-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Geng-Cing LIN ,  Ze-Sian LU ,  Meng-Sheng CHANG ,  Chia-En HUANG ,  Jung-Ping YANG ,  Yen-Huei CHEN

IPC: H01L27/112 ,  H01L23/528 ,  H01L21/265

Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.