公开(公告)号：US20210036012A1

公开(公告)日：2021-02-04

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L21/02

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20230180477A1

公开(公告)日：2023-06-08

申请号：US18161331

申请日：2023-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun YANG ,  Bio KIM ,  Yujin KIM ,  Kyong-won AN ,  Sookyeom YONG ,  Junggeun LEE ,  Youngjun CHEON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US20220238555A1

公开(公告)日：2022-07-28

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20200350332A1

公开(公告)日：2020-11-05

申请号：US16930711

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung CHOI ,  Hyung Joon KIM ,  Bio KIM ,  Yujin KIM ,  Junggeun JEE

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/1157

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US20250079238A1

公开(公告)日：2025-03-06

申请号：US18762397

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uihyoung LEE ,  Sang Ho JIN ,  Jongguk PARK ,  Yujin KIM ,  Hakyung YUN ,  Wonhee LEE

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of fabricating a semiconductor device is provided. The method includes: providing an interlayer dielectric layer with a trench on a substrate in a first substrate processing apparatus in a vacuum state; forming a first metal barrier in the trench while the substrate is in the first substrate processing apparatus; unloading the substrate from the first substrate processing apparatus and exposing the substrate to a non-vacuum environment; providing the substrate in a second substrate processing apparatus of a vacuum state; forming a second metal barrier in the trench in the second substrate processing apparatus; and forming a metal pattern to fill the trench.