公开(公告)号：US20220375932A1

公开(公告)日：2022-11-24

申请号：US17880819

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L23/538

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20240162226A1

公开(公告)日：2024-05-16

申请号：US18416375

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L23/5384 ,  H01L29/0653 ,  H01L29/4232

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20240321726A1

公开(公告)日：2024-09-26

申请号：US18419715

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Yubo QIAN ,  Hyunjae KANG ,  Gyeongseop KIM ,  Sutae KIM ,  Jaeyoung PARK ,  Jeonwon JEONG

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L27/0886

Abstract: An integrated circuit device includes a first conductive pattern disposed on a substrate, a second conductive pattern surrounding a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulation structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern penetrating through the upper insulation structure and extending in a vertical direction, wherein the upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension extending from a portion of the main plug portion toward the substrate, covering an upper of the upper sidewall of the first conductive pattern, and overlapping the second conductive pattern in the vertical direction, and a dummy contact is formed on a single diffusion break region on the substrate.

公开(公告)号：US20210175232A1

公开(公告)日：2021-06-10

申请号：US17024044

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah NAM ,  Byungju KANG ,  Byungsung KIM ,  Hyelim KIM ,  Sungho PARK ,  Yubo QIAN

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.