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公开(公告)号：US11870399B2
公开(公告)日：2024-01-09
申请号：US17227996
申请日：2021-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunghwan Hong , Youngsoo Sohn , Jeongdon Ihm , Changhyun Bae , Yoochang Sung
CPC classification number: H03F1/26 , H03F3/19 , H03F2200/375
Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.
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Patent Agency Ranking
2.发明授权公开(公告)号：US12216909B2
公开(公告)日：2025-02-04
申请号：US17992516
申请日：2022-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taekwoon Kim , Youngsoo Sohn
IPC: G06F3/06
Abstract: A memory module including a row hammer counter chip, a memory system including the same, and a method of operating the memory system are provided. The memory module includes a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.
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3.发明授权公开(公告)号：US09385730B2
公开(公告)日：2016-07-05
申请号：US14272975
申请日：2014-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan Bae , Kee-won Kwon , Kyoungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。
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4.发明公开公开(公告)号：US20230205428A1
公开(公告)日：2023-06-29
申请号：US17992516
申请日：2022-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taekwoon KIM , Youngsoo Sohn
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0673
Abstract: A memory module including a row hammer counter chip, a memory system including the same, and a method of operating the memory system are provided. The memory module includes a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.
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公开(公告)号：US11334457B1
公开(公告)日：2022-05-17
申请号：US16839675
申请日：2020-04-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hohyun Shin , Jongwan Kim , Hyungi Kim , Hyunsung Shin , Dongmin Kim , Myeongo Kim , Kwangil Park , Youngsoo Sohn
Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.
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公开(公告)号：US09654118B2
公开(公告)日：2017-05-16
申请号：US15179202
申请日：2016-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan Bae , Kee-Won Kwon , Kyungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
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