公开(公告)号：US20220368328A1

公开(公告)日：2022-11-17

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jinhyeok BAEK ,  Yoochang SUNG ,  Changsik YOO ,  Jeongdon IHM

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US20230032415A1

公开(公告)日：2023-02-02

申请号：US17722805

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jaewoo JEONG ,  Kyungryun KIM ,  Yoochang SUNG ,  Changsik YOO

IPC: G11C7/10

Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

公开(公告)号：US20240282269A1

公开(公告)日：2024-08-22

申请号：US18437668

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongim LEE ,  Yonghun KIM ,  Junkwan PARK

IPC: G09G3/3275

CPC classification number: G09G3/3275 ,  G09G2330/021

Abstract: A source driver is provided. The source driver includes: a switch circuit with first switches, which are respectively connected between a first charge sharing line and data lines; and a charge sharing controller configured to: receive pieces of first pixel data, which respectively correspond to the data lines, and pieces of second pixel data, which respectively correspond to the of first pixel data; output a charge sharing signal having an active level to a first group of switches among the first switches respectively connected to first data lines from among the lines, based on the pieces of first pixel data and the pieces of second pixel data corresponding to the first data lines being different from each other in at least two upper bits thereof.

公开(公告)号：US20240144991A1

公开(公告)日：2024-05-02

申请号：US18326657

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo JEONG ,  Yonghun KIM ,  Kihan KIM ,  Changsik YOO

IPC: G11C11/4076 ,  G06F1/10 ,  G06F1/12

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F1/12

Abstract: A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.