公开(公告)号：US20190355822A1

公开(公告)日：2019-11-21

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG CHAI JUNG ,  MYUNG GIL KANG ,  KANG ILL SEO ,  SEON BAE KIM ,  YONG HEE PARK

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

公开(公告)号：US20220037527A1

公开(公告)日：2022-02-03

申请号：US17474217

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG CHAI JUNG ,  Seon Bae KIM ,  Seung Hyun SONG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L27/085

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US20210111270A1

公开(公告)日：2021-04-15

申请号：US16798482

申请日：2020-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANG WOO SOHN ,  SEUNG HYUN SONG ,  SEON-BAE KIM ,  MIN CHEOL OH ,  YOUNG CHAI JUNG

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.