公开(公告)号：US20220302588A1

公开(公告)日：2022-09-22

申请号：US17682615

申请日：2022-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghue HONG ,  Jaewan PARK ,  Minsung KOO ,  Minsoo SOHN ,  Woosung LEE

IPC: H01Q5/35 ,  H01Q1/42 ,  H01Q1/24 ,  H01Q5/314

Abstract: An electronic device is provided. The electronic device includes an antenna, a wireless communication module electrically connected to the antenna, a flexible printed circuit board (FPCB) including a first feeding element and a second feeding element which are electrically connected to the wireless communication module, a substrate disposed above the first feeding element and the second feeding element, a first conductive pattern including a first coupling hole and a second conductive pattern including a second coupling hole, which are formed on the upper surface of the substrate, a first coupling fastener configured to penetrate the first coupling hole and the first feeding element and electrically connect the first conductive pattern and the first feeding element, and a second coupling fastener configured to penetrate the second coupling hole and the second feeding element and electrically connect the second conductive pattern and the second feeding element.

公开(公告)号：US20210265373A1

公开(公告)日：2021-08-26

申请号：US17034274

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinjae KANG ,  Woosung LEE ,  Jeonggil LEE ,  Hanmei CHOI ,  Hauk HAN

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

公开(公告)号：US20220199122A1

公开(公告)日：2022-06-23

申请号：US17694946

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosung LEE ,  Chunghyun RYU ,  Hyoungtaek LIM

IPC: G11C5/00 ,  G11C5/14

Abstract: A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

公开(公告)号：US20230292509A1

公开(公告)日：2023-09-14

申请号：US18072276

申请日：2022-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeong YANG ,  Yuyeon KIM ,  Woosung LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H01L23/528 ,  H10B41/35 ,  H10B43/35 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure by stacking interlayer insulating layers alternately with sacrificial layers on a plate layer, forming channel holes passing through the molded structure, forming channel layers doped with non-conductive impurities in the channel holes, forming a metal layer above the channel holes, forming metal silicide layers on upper ends of the channel layers using the metal layer, crystallizing the channel layers using the metal silicide layers by performing a heat treatment process at a temperature of 800 degrees or more, forming openings penetrating through the molded structure and extending in one direction, removing the sacrificial layers exposed through the openings, and forming gate electrodes, by filling regions from which the sacrificial layers have been removed, with a conductive material. After the crystallizing, the metal silicide layers are located lower than a lowermost gate electrode among the gate electrodes.