公开(公告)号：US20170117192A1

公开(公告)日：2017-04-27

申请号：US15215951

申请日：2016-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki Min ,  Gi-Gwan PARK ,  Sang-Koo KANG ,  Sung-Sao KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jae-Hoon LEE ,  Tae-Won HA

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7854

Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.