公开(公告)号：US20240079349A1

公开(公告)日：2024-03-07

申请号：US18334578

申请日：2023-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Younglyong Kim ,  Seungbin Baek

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/36 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L23/36 ,  H01L23/5385 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204

Abstract: A semiconductor package is provided to include a package substrate, a plurality of semiconductor chips mounted on the package substrate, an interposer arranged between the package substrate and the plurality of semiconductor chips, a plurality of passive elements mounted on the package substrate and spaced apart from the interposer, a first stiffener positioned on the package substrate and including a first hole accommodating the interposer and a second hole accommodating the plurality of passive elements, and a second stiffener positioned on the first stiffener and including a third hole communicating with the first hole. The first stiffener has a first coefficient of thermal expansion, and the second stiffener has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

公开(公告)号：US20220415772A1

公开(公告)日：2022-12-29

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US12272628B2

公开(公告)日：2025-04-08

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US12237241B2

公开(公告)日：2025-02-25

申请号：US17718662

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Jisun Yang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.