公开(公告)号：US20230290727A1

公开(公告)日：2023-09-14

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/34 ,  H10B12/48 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US11740553B2

公开(公告)日：2023-08-29

申请号：US17510665

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hungbae Ahn ,  Sangoh Park ,  Sunggon Jung

IPC: H01L21/033 ,  H01L21/768 ,  H10B12/00 ,  G03F1/70

CPC classification number: G03F1/70 ,  H01L21/0332 ,  H01L21/76895 ,  H10B12/03 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.

公开(公告)号：US12237265B2

公开(公告)日：2025-02-25

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20220262731A1

公开(公告)日：2022-08-18

申请号：US17487460

申请日：2021-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Hyunseo Shin ,  Seokhan Park ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure.

公开(公告)号：US11226552B2

公开(公告)日：2022-01-18

申请号：US16872444

申请日：2020-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hungbae Ahn ,  Sangoh Park ,  Sunggon Jung

IPC: H01L27/108 ,  H01L21/033 ,  H01L21/768 ,  G03F1/70

Abstract: A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.

公开(公告)号：US12260164B2

公开(公告)日：2025-03-25

申请号：US17703338

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hungbae Ahn ,  Sangoh Park ,  Jinho Lee

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: A pattern layout design method includes performing optical proximity correction (OPC) for a mask layout, thereby creating a corrected layout. Creation of the corrected layout includes creating a first corrected layout through grid snapping for an oblique edge of a mask layout designed on a grid layout, and performing optical proximity correction (OPC) for the first corrected layout, thereby creating a second corrected layout. Creation of the first corrected layout includes creating a first divisional point for the oblique edge or a residual edge, and shifting the first divisional point to one of four reference points adjacent to the first divisional point, thereby creating a first varied divisional point.

公开(公告)号：US11688687B2

公开(公告)日：2023-06-27

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US11506983B2

公开(公告)日：2022-11-22

申请号：US17185140

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hungbae Ahn ,  Sangoh Park ,  Seunghune Yang

IPC: G03F7/20 ,  H01L27/02

Abstract: A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

公开(公告)号：US20220037251A1

公开(公告)日：2022-02-03

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.