公开(公告)号：US20220173119A1

公开(公告)日：2022-06-02

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/108

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20240179912A1

公开(公告)日：2024-05-30

申请号：US18436169

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20220320025A1

公开(公告)日：2022-10-06

申请号：US17529462

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jiyoung KIM ,  Sanghee YOON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.