Semiconductor device, layout design method for the same and method for fabricating the same

    公开(公告)号:US12068251B2

    公开(公告)日:2024-08-20

    申请号:US17449721

    申请日:2021-10-01

    CPC classification number: H01L23/5286 H01L23/481 H01L27/092 H01L27/0924

    Abstract: A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.

    SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20220223523A1

    公开(公告)日:2022-07-14

    申请号:US17449721

    申请日:2021-10-01

    Abstract: A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.

    METHOD AND APPARATUS FOR ESTIMATING BATTERY LIFE DURING DRIVING OF ELECTRICAL VEHICLE (EV)
    7.
    发明申请
    METHOD AND APPARATUS FOR ESTIMATING BATTERY LIFE DURING DRIVING OF ELECTRICAL VEHICLE (EV) 有权
    用于在电动车辆驾驶期间估算电池寿命的方法和装置(EV)

    公开(公告)号:US20150301121A1

    公开(公告)日:2015-10-22

    申请号:US14489857

    申请日:2014-09-18

    Inventor: Sang Do Park

    CPC classification number: G01R31/3679 G01R31/3662

    Abstract: An apparatus for estimating a battery life includes a battery monitor configured to monitor an output signal from a battery; a steady state detector configured to detect a first steady state in which the output signal stays in a steady state and a second steady state differing from the first steady state; and an estimator configured to estimate a battery life from a variation of the output signal in a transient state in which the output signal transitions from the first steady state to the second steady state.

    Abstract translation: 用于估计电池寿命的装置包括:电池监视器,被配置为监视来自电池的输出信号; 稳态检测器,被配置为检测其中输出信号保持在稳定状态的第一稳态和与第一稳态不同的第二稳态; 以及估计器,被配置为在输出信号从第一稳定状态转变到第二稳定状态的瞬态状态下从输出信号的变化估计电池寿命。

    Semiconductor device including hard macro

    公开(公告)号:US12293958B2

    公开(公告)日:2025-05-06

    申请号:US17236018

    申请日:2021-04-21

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which comprises a first surface and a second surface opposing each other, and a hard macro which is disposed on the first surface of the substrate. The hard macro comprises a cell area and a halo area formed along the periphery of the cell area. In addition, the hard macro comprises a first connection wiring disposed at a first metal level and having at least a part extending from the cell area to the halo area, a first power rail which is disposed on the second surface of the substrate and receives a first voltage, and a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring and is a single structure.

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