公开(公告)号：US20220223523A1

公开(公告)日：2022-07-14

申请号：US17449721

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hyun Lee ,  Sung-Ok Lee ,  Sang Do Park

IPC: H01L23/528 ,  H01L27/092 ,  H01L23/48

Abstract: A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.

公开(公告)号：US12068251B2

公开(公告)日：2024-08-20

申请号：US17449721

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hyun Lee ,  Sung-Ok Lee ,  Sang Do Park

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.