公开(公告)号：US20240194488A1

公开(公告)日：2024-06-13

申请号：US18243185

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young LEE ,  Jong Doo Kim ,  Ju Yun Park

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/308 ,  H01L29/66439 ,  H01L29/66545

Abstract: A method for manufacturing a mask pattern includes forming a mold mask layer on a substrate. A pre-mold mask pattern that includes a first trench extending in a first direction is formed by etching the mold mask layer. The first trench has a first width in a second direction crossing the first direction. A mold mask pattern that includes a second trench connected to the first trench is formed by etching the pre-mold mask pattern. The second trench has a second width different from the first width in the second direction. The second trench is adjacent to the first trench in the first direction. A process mask pattern that fills the first and second trenches is formed in the mold mask pattern and disposed on the substrate. The mold mask pattern is removed and the process mask pattern remains disposed on the substrate after removing the mold mask pattern.

公开(公告)号：US11037842B2

公开(公告)日：2021-06-15

申请号：US16412306

申请日：2019-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Doo Kim

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor device includes a first normal pattern which is disposed in an active area of a semiconductor chip, wherein the first normal pattern has a particular shape and the active area includes circuitry for operating the semiconductor chip, and includes a first defective pattern and a second normal pattern which are disposed in a dummy area of the semiconductor chip, wherein the dummy area of the semiconductor chip is an area that does not perform functions for operating the semiconductor chip. The second normal pattern has the same shape as the first normal pattern and the first defective pattern has the same shape as the first normal pattern except for a first defect. The first normal pattern is disposed at a first level layer of the semiconductor chip. The first defective pattern comprises a first part and a second part, and the second normal pattern comprises a third part corresponding to the first part and that matches the first part in shape and size and a fourth part corresponding to the second part, wherein the second part includes the first defect and matches the fourth part in shape and size except for the first defect. If the second part and fourth part were to be superimposed over each other, the second part would include a piece of material that is absent from the fourth part and that comprises the first defect.

公开(公告)号：US12293958B2

公开(公告)日：2025-05-06

申请号：US17236018

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Doo Kim ,  Sang Do Park

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which comprises a first surface and a second surface opposing each other, and a hard macro which is disposed on the first surface of the substrate. The hard macro comprises a cell area and a halo area formed along the periphery of the cell area. In addition, the hard macro comprises a first connection wiring disposed at a first metal level and having at least a part extending from the cell area to the halo area, a first power rail which is disposed on the second surface of the substrate and receives a first voltage, and a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring and is a single structure.