公开(公告)号：US10510658B2

公开(公告)日：2019-12-17

申请号：US16039838

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Deok Young Jung ,  Sang Bom Kang ,  Doo-Hwan Park ,  Jong Min Baek ,  Sang Hoon Ahn ,  Hyeok Sang Oh ,  Woo Kyung You

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

公开(公告)号：US10388563B2

公开(公告)日：2019-08-20

申请号：US15668029

申请日：2017-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rak Hwan Kim ,  Byung Hee Kim ,  Sang Bom Kang ,  Jong Jin Lee ,  Eun Ji Jung

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.