公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20240292600A1

公开(公告)日：2024-08-29

申请号：US18240516

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Tae RYU ,  Byong-Deok CHOI ,  Sungwon YOO ,  Wonsok LEE ,  Yongsang YOO

IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: H10B12/482 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L28/90 ,  H10B12/312 ,  H10B12/315 ,  H10B12/50

Abstract: A memory device includes a first memory cell connected to a first bitline and a second memory cell connected to a second bitline, wherein the first memory cell may include a first access transistor including one end connected to the first bitline, and a first capacitor including one electrode connected to another end of the first access transistor and another electrode connected to the second bitline, and the first access transistor may include an oxide semiconductor.

公开(公告)号：US20230307551A1

公开(公告)日：2023-09-28

申请号：US18092973

申请日：2023-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwon YOO ,  Yongseok KIM ,  Min Tae RYU ,  Huije RYU ,  Yongjin LEE ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L29/786 ,  H10B12/00 ,  H01L27/146 ,  H01L29/417

CPC classification number: H01L29/78693 ,  H01L27/10814 ,  H01L27/14616 ,  H01L29/41733 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.

公开(公告)号：US20240371994A1

公开(公告)日：2024-11-07

申请号：US18775518

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20220367721A1

公开(公告)日：2022-11-17

申请号：US17694903

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Kyeong JEONG ,  Min Tae RYU ,  Hyeon Joo SEUL ,  Sungwon YOO ,  Wonsok LEE ,  Min Hee CHO ,  Jae Seok HUR

IPC: H01L29/786

Abstract: Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

公开(公告)号：US20220223732A1

公开(公告)日：2022-07-14

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H01L27/108

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.