公开(公告)号：US11996065B2

公开(公告)日：2024-05-28

申请号：US17985599

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Yongyun Park ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2370/04

Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.

公开(公告)号：US09959835B2

公开(公告)日：2018-05-01

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Baek ,  Hyunwook Lim ,  Kwi Sung Yoo ,  Eun-Young Jin ,  Kyongho Kim ,  JaeYoul Lee ,  Youngmin Choi

IPC: G09G5/00 ,  H03L7/08 ,  H03L7/089 ,  G09G3/20

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

公开(公告)号：US11223468B1

公开(公告)日：2022-01-11

申请号：US17194831

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim ,  Younghwan Chang ,  Sengsub Chun

IPC: H04L7/00 ,  H04L27/01

Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

公开(公告)号：US11996935B2

公开(公告)日：2024-05-28

申请号：US18146732

申请日：2022-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho Kim ,  Changsik Yoo ,  Kyungmin Kim

IPC: H04L7/00 ,  H04L1/00

CPC classification number: H04L1/0042 ,  H04L1/0048 ,  H04L1/0061

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US11552730B2

公开(公告)日：2023-01-10

申请号：US17144425

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho Kim ,  Changsik Yoo ,  Kyungmin Kim

IPC: H04L1/00

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US10885870B2

公开(公告)日：2021-01-05

申请号：US16814535

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyongho Kim ,  Jinho Kim ,  Jaeyoul Lee ,  Hyunwook Lim ,  Youngmin Choi

IPC: G09G5/00

Abstract: An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.