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    MEMORY CONTROLLER MANAGING REFRESH OPERATION AND OPERATING METHOD THEREOF
    1.
    发明公开
    MEMORY CONTROLLER MANAGING REFRESH OPERATION AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240249793A1

    公开(公告)日：2024-07-25

    申请号：US18394627

    申请日：2023-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin YOU ,  Eunae LEE ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Kyomin SOHN

    IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408

    CPC classification number: G11C29/52 ,  G11C11/40615 ,  G11C11/4085

    Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE 有权

    公开(公告)号：US20210157751A1

    公开(公告)日：2021-05-27

    申请号：US16934497

    申请日：2020-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hyuk KWON ,  Nam Sung KIM ,  Kyomin SOHN ,  Jaeyoun YOUN

    IPC: G06F13/16 ,  H01L25/065

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
    5.
    发明公开
    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE 审中-公开

    公开(公告)号：US20240086345A1

    公开(公告)日：2024-03-14

    申请号：US18511725

    申请日：2023-11-16

    Applicant: SAMSUNG ELECTRONICS Co., LTD.

    Inventor： Sang-Hyuk KWON ,  Nam Sung KIM ,  Kyomin SOHN ,  Jaeyoun YOUN

    IPC: G06F13/16 ,  H01L25/065

    CPC classification number: G06F13/1668 ,  H01L25/0657 ,  G11C8/10

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

    MEMORY DEVICE, MEMORY MODULE, AND OPERATING METHOD OF MEMORY DEVICE FOR PROCESSING IN MEMORY
    6.
    发明公开
    MEMORY DEVICE, MEMORY MODULE, AND OPERATING METHOD OF MEMORY DEVICE FOR PROCESSING IN MEMORY 审中-公开

    公开(公告)号：US20230223065A1

    公开(公告)日：2023-07-13

    申请号：US18070741

    申请日：2022-11-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Shinhaeng KANG ,  Kyomin SOHN

    IPC: G11C11/22

    CPC classification number: G11C11/2257 ,  G11C11/2275

    Abstract: Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

    MEMORY DEVICE INCLUDING INTERFACE CIRCUIT FOR DATA CONVERSION ACCORDING TO DIFFERENT ENDIAN FORMATS
    9.
    发明申请
    MEMORY DEVICE INCLUDING INTERFACE CIRCUIT FOR DATA CONVERSION ACCORDING TO DIFFERENT ENDIAN FORMATS 有权

    公开(公告)号：US20210365203A1

    公开(公告)日：2021-11-25

    申请号：US17213732

    申请日：2021-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongil O ,  Jongpil SON ,  Kyomin SOHN

    IPC: G06F3/06

    Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

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