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    MEMORY CONTROLLER MANAGING REFRESH OPERATION AND OPERATING METHOD THEREOF
    2.
    发明公开
    MEMORY CONTROLLER MANAGING REFRESH OPERATION AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240249793A1

    公开(公告)日：2024-07-25

    申请号：US18394627

    申请日：2023-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin YOU ,  Eunae LEE ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Kyomin SOHN

    IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408

    CPC classification number: G11C29/52 ,  G11C11/40615 ,  G11C11/4085

    Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

    MEMORY DEVICE DETECTING WEAKNESS OF OPERATION PATTERN AND METHOD OF OPERATING THE SAME
    3.
    发明公开
    MEMORY DEVICE DETECTING WEAKNESS OF OPERATION PATTERN AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230178136A1

    公开(公告)日：2023-06-08

    申请号：US18052469

    申请日：2022-11-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin YOU

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4085

    Abstract: Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230111467A1

    公开(公告)日：2023-04-13

    申请号：US17731994

    申请日：2022-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin CHO ,  Jungmin YOU

    IPC: G11C29/20 ,  G11C29/44 ,  G11C29/00

    Abstract: A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE
    6.
    发明公开
    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240233801A1

    公开(公告)日：2024-07-11

    申请号：US18610420

    申请日：2024-03-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin YOU ,  Wonhyung SONG ,  Hoyoun KIM

    IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

    CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230101739A1

    公开(公告)日：2023-03-30

    申请号：US17724942

    申请日：2022-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin YOU ,  Seongjin Cho

    IPC: G11C11/406 ,  G11C11/4093

    Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

    MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE INCLUDING ROW HAMMER PREVENTING CIRCUITRY AND AN OPERATING METHOD OF THE MEMORY DEVICE 有权

    公开(公告)号：US20230079457A1

    公开(公告)日：2023-03-16

    申请号：US17939327

    申请日：2022-09-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin YOU

    IPC: G11C11/406 ,  G11C11/4078

    Abstract: A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.

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