公开(公告)号：US20230045674A1

公开(公告)日：2023-02-09

申请号：US17662306

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

公开(公告)号：US20250159861A1

公开(公告)日：2025-05-15

申请号：US18825173

申请日：2024-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keonhee Park ,  Haewook Jeong

IPC: H10B12/00

Abstract: A semiconductor device includes first and second bit lines, a word line, first and second channels and a capacitor. The first and second bit lines extend primarily in a first direction and are spaced apart from each other in a second direction on a substrate. The word line includes first extension portions extending primarily in a third direction, between the first and second bit lines, and a second extension portion extending primarily in the second direction at the same level as the first extension portions and is connected thereto. Each of the first and second channels extends through the first extension portions. The capacitor includes a first capacitor electrode electrically connected to the first channel, a dielectric pattern disposed on a surface of the first capacitor electrode, and a second capacitor electrode disposed on a surface of the dielectric pattern and electrically connected to the second channel.

公开(公告)号：US12302556B2

公开(公告)日：2025-05-13

申请号：US17747423

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang ,  Hyeon-Woo Jang

IPC: H01L27/108 ,  H01L21/3213 ,  H10B12/00

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.

公开(公告)号：US20240196594A1

公开(公告)日：2024-06-13

申请号：US18478978

申请日：2023-09-29

Applicant: Samsung Electronics Co .,LTD

Inventor： Hyeri AN ,  Dongsik Park ,  Sooho Shain ,  Joonsuk Park ,  Keonhee Park ,  Gaeun Lee ,  Jihoon Chang ,  Yujin Cho ,  Hana Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/01

Abstract: A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %.

公开(公告)号：US20230039205A1

公开(公告)日：2023-02-09

申请号：US17723747

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-sik Park ,  Joonsuk Park ,  Jihoon Chang

IPC: H01L27/108

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.