公开(公告)号：US20170345822A1

公开(公告)日：2017-11-30

申请号：US15676317

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kee Sang Kwon ,  Boun YOON ,  Sangjine PARK ,  Myunggeun SONG ,  Ki-Hyung KO ,  Jiwon YUN

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49

Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US10714472B2

公开(公告)日：2020-07-14

申请号：US15676317

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US09960241B2

公开(公告)日：2018-05-01

申请号：US14989485

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.