公开(公告)号：US20220361339A1

公开(公告)日：2022-11-10

申请号：US17591734

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwa KIM ,  Junso PAK ,  Heeseok LEE ,  Moonseob JEONG ,  Jisoo HWANG

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H05K1/02

Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

公开(公告)号：US20250157867A1

公开(公告)日：2025-05-15

申请号：US18883053

申请日：2024-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkook KIM ,  Heungkyu KWON ,  Youngchul KIM ,  Choonheung LEE ,  Donghyun CHA ,  Junghwa KIM ,  Junso PAK ,  Kyounghoon LEE ,  Jaegwon JANG ,  Hangchul CHOI ,  Heejung CHOI ,  Kyojin HWANG

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: A semiconductor package that includes an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on which the upper package is mounted in a central region; and a stiffener positioned on a top surface of the PCB and including an opening. A top surface of the PCB contacts a bottom surface of the stiffener in at least part of edge regions of the PCB. In the central region of the PCB and in edge regions other than the at least part of edge regions of the PCB, a top surface of the PCB is apart from the bottom surface of the stiffener in a vertical direction, and the opening of the stiffener overlaps the upper package in the vertical direction.

公开(公告)号：US20220181288A1

公开(公告)日：2022-06-09

申请号：US17542667

申请日：2021-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung CHOI ,  Heeseok LEE ,  Junso PAK ,  Bongwee YU

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

公开(公告)号：US20210028100A1

公开(公告)日：2021-01-28

申请号：US16863257

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junso PAK ,  Seungki NAM ,  Jiyoung PARK ,  Bo PU

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.