公开(公告)号：US20210248003A1

公开(公告)日：2021-08-12

申请号：US17112008

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul SEOK ,  Choonghoon PARK ,  Byungsoo KWON ,  Bumgyu PARK ,  Jonglae PARK ,  Junhwa SEO ,  Youngcheol SHIN ,  Youngtae LEE

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

Abstract: An apparatus and a method for scheduling a task in an electronic device including a heterogeneous multi-processor are provided. The electronic device includes a memory and a processor operatively connected to the memory and including a plurality of heterogeneous cores. The processor may be configured to identify, when a task to be scheduled occurs, a scheduling group having the task among a plurality of predefined scheduling groups, and to perform scheduling for the task, based on the identified scheduling group having the task and a priority of the task.

公开(公告)号：US20230043222A1

公开(公告)日：2023-02-09

申请号：US17866923

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Donghee HAN

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/445

Abstract: An apparatus includes a plurality of processing cores, and a memory including a plurality of task queues corresponding to the plurality of processing cores, respectively, wherein at least one processing core of the plurality of processing cores is configured, by executing a scheduler, to determine execution of task rescheduling, based on states of the plurality of processing cores, tasks stored in the plurality of task queues, and at least one reference value, and, when the task rescheduling is executed, move a first task stored in a first task queue to a second task queue.

公开(公告)号：US20240061492A1

公开(公告)日：2024-02-22

申请号：US18180427

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Daeyeong LEE ,  Jiyoung LEE ,  Hyunwook JOO

IPC: G06F1/3234 ,  G06F1/20

CPC classification number: G06F1/3275 ,  G06F1/206

Abstract: A processor includes a central processing unit (CPU) configured to drive a dynamic voltage and frequency scaling (DVFS) module, a memory hierarchy configured to store data for an operation of the CPU, and an activity monitoring unit (AMU) configured to generate microarchitecture information by monitoring performance of the CPU or monitoring traffic of a system bus connected to the memory hierarchy. The DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to increase a frequency in response to the determined layer being accessed.

公开(公告)号：US20210057420A1

公开(公告)日：2021-02-25

申请号：US16823483

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu KIM ,  Jonglae PARK ,  Hyunju KANG ,  Jungwook KIM

IPC: H01L27/112 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/12

Abstract: There is provided a method of controlling performance boosting of a semiconductor device. According to the method, input of a user is monitored. A performance of the semiconductor device is boosted by consecutively executing a plurality of boosting policies associated with a plurality of macros based on an input event associated with the input of the user and available energy during a boosting interval. Boosting level in each of the boosting policies may be adaptively determined based on the boosting level and the amount of usage of the semiconductor device used in the previous boosting policy and the boosting policies are consecutively executed. Accordingly, improved and/or optimal performance boosting can be provided to the semiconductor device and at the same time, a waste of power can be mitigated and/or prevented.

公开(公告)号：US20240338250A1

公开(公告)日：2024-10-10

申请号：US18392956

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunok JO ,  Jonglae PARK ,  Sangkyu KIM ,  Bumgyu PARK

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: An electronic system includes a multi-core processor including a plurality of cores; a performance index logger configured to log a performance index per core for a plurality of tasks allocated to the multi-core processor, respectively; a target core selector configured to calculate a suitability index based on a performance index per core for a target task from among the plurality of tasks, and based on an index per core determined independently of the target task, and to select a target core based on the suitability index; and a task allocator configured to allocate the target task to the target core.

公开(公告)号：US20230214271A1

公开(公告)日：2023-07-06

申请号：US17888162

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu KIM ,  Jonglae PARK ,  Yeonghwan SON ,  Dahye CHOI

IPC: G06F9/50 ,  G06F12/0877

CPC classification number: G06F9/505 ,  G06F12/0877 ,  G06F2212/6042

Abstract: A method is provided. The method includes: receiving a plurality of characteristic information associated with a plurality of tasks allocated to a plurality of processor cores; monitoring a task execution environment while the plurality of processor cores perform the plurality of tasks based on at least one operating condition; and allocating a plurality of cache areas of at least one cache memory to the plurality of processor cores based on the plurality of characteristic information and the task execution environment. Sizes of the plurality of cache areas are set differently for the plurality of processor cores.

公开(公告)号：US20220187866A1

公开(公告)日：2022-06-16

申请号：US17498019

申请日：2021-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonglae PARK ,  Hanjun SHIN ,  Hyunji HONG ,  Choonghoon PARK

IPC: G06F1/08

Abstract: An electronic device includes a clock management unit configured to generate a clock signal, an intellectual property (IP) device configured to receive the clock signal and is configured to perform a task according to the clock signal in an active state, a first counter configured to count cycles of the clock signal while the IP device is in the active state, and is configured to generate a first count, and a frequency controller configured to control the clock management unit to change a frequency of the clock signal when the first count reaches a first reference count.