公开(公告)号：US20240061492A1

公开(公告)日：2024-02-22

申请号：US18180427

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Daeyeong LEE ,  Jiyoung LEE ,  Hyunwook JOO

IPC: G06F1/3234 ,  G06F1/20

CPC classification number: G06F1/3275 ,  G06F1/206

Abstract: A processor includes a central processing unit (CPU) configured to drive a dynamic voltage and frequency scaling (DVFS) module, a memory hierarchy configured to store data for an operation of the CPU, and an activity monitoring unit (AMU) configured to generate microarchitecture information by monitoring performance of the CPU or monitoring traffic of a system bus connected to the memory hierarchy. The DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to increase a frequency in response to the determined layer being accessed.