公开(公告)号：US20240061492A1

公开(公告)日：2024-02-22

申请号：US18180427

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Daeyeong LEE ,  Jiyoung LEE ,  Hyunwook JOO

IPC: G06F1/3234 ,  G06F1/20

CPC classification number: G06F1/3275 ,  G06F1/206

Abstract: A processor includes a central processing unit (CPU) configured to drive a dynamic voltage and frequency scaling (DVFS) module, a memory hierarchy configured to store data for an operation of the CPU, and an activity monitoring unit (AMU) configured to generate microarchitecture information by monitoring performance of the CPU or monitoring traffic of a system bus connected to the memory hierarchy. The DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to increase a frequency in response to the determined layer being accessed.

公开(公告)号：US20240338250A1

公开(公告)日：2024-10-10

申请号：US18392956

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunok JO ,  Jonglae PARK ,  Sangkyu KIM ,  Bumgyu PARK

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: An electronic system includes a multi-core processor including a plurality of cores; a performance index logger configured to log a performance index per core for a plurality of tasks allocated to the multi-core processor, respectively; a target core selector configured to calculate a suitability index based on a performance index per core for a target task from among the plurality of tasks, and based on an index per core determined independently of the target task, and to select a target core based on the suitability index; and a task allocator configured to allocate the target task to the target core.

公开(公告)号：US20240320061A1

公开(公告)日：2024-09-26

申请号：US18528160

申请日：2023-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumgyu PARK ,  Jonglae Park ,  Sangkyu Kim ,  Eunok Jo

IPC: G06F9/52

CPC classification number: G06F9/526

Abstract: Provided is a method of controlling access a shared resources when executing a first process that acquires a lock on the shared resource and adding a second process to a waiting queue. A determination is made on whether to deactivate preemption for the processor based on a priority of the second process, and based on determining to deactivate preemption for the processor, executing the first process until execution of the first process on the shared resource is completed, then retrieving the lock from the first process after execution of the first process on the shared resource is completed and reactivating preemption for the processor.

公开(公告)号：US20210248003A1

公开(公告)日：2021-08-12

申请号：US17112008

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul SEOK ,  Choonghoon PARK ,  Byungsoo KWON ,  Bumgyu PARK ,  Jonglae PARK ,  Junhwa SEO ,  Youngcheol SHIN ,  Youngtae LEE

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

Abstract: An apparatus and a method for scheduling a task in an electronic device including a heterogeneous multi-processor are provided. The electronic device includes a memory and a processor operatively connected to the memory and including a plurality of heterogeneous cores. The processor may be configured to identify, when a task to be scheduled occurs, a scheduling group having the task among a plurality of predefined scheduling groups, and to perform scheduling for the task, based on the identified scheduling group having the task and a priority of the task.

公开(公告)号：US20240086234A1

公开(公告)日：2024-03-14

申请号：US18196749

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Eunok JO ,  Bumgyu PARK ,  Seyeong BYEON ,  Daeyeong LEE

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: An electronic device includes: a plurality of processing cores and a memory including a plurality of task queues respectively corresponding to the plurality of processing cores and a plurality of task relation tables respectively corresponding to a plurality of tasks. Each of the plurality of task relation tables includes: one or more entries representing a mapping relationship between an identifier of a waker task that wakes up a wakee task, and an occurrence count that is a number of times the wakee task is woken up by the waker task. At least one of the plurality of processing cores is configured to: execute a scheduler, search for a task set includes related tasks, based on the plurality of task relation tables, store a subset of tasks of the task set in at least one of the plurality of task queues, and schedule the task set.

公开(公告)号：US20230043222A1

公开(公告)日：2023-02-09

申请号：US17866923

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Donghee HAN

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/445

Abstract: An apparatus includes a plurality of processing cores, and a memory including a plurality of task queues corresponding to the plurality of processing cores, respectively, wherein at least one processing core of the plurality of processing cores is configured, by executing a scheduler, to determine execution of task rescheduling, based on states of the plurality of processing cores, tasks stored in the plurality of task queues, and at least one reference value, and, when the task rescheduling is executed, move a first task stored in a first task queue to a second task queue.