公开(公告)号：US09728463B2

公开(公告)日：2017-08-08

申请号：US15209093

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin Lim ,  Gi-gwan Park ,  Sang-yub Ie ,  Jong-han Lee ,  Jeong-hyuk Yim ,  Hye-ri Hong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/823462 ,  H01L21/02123 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/3003 ,  H01L21/67207 ,  H01L29/66795

Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

公开(公告)号：US20190189767A1

公开(公告)日：2019-06-20

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol SONG ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

公开(公告)号：US10529817B2

公开(公告)日：2020-01-07

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.