PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME

    公开(公告)号:US20200349985A1

    公开(公告)日:2020-11-05

    申请号:US16934134

    申请日:2020-07-21

    Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

    USER EQUIPMENT, SERVER, CONTROL METHOD OF THE USER EQUIPMENT AND CONTROL METHOD OF THE SERVER

    公开(公告)号:US20200159554A1

    公开(公告)日:2020-05-21

    申请号:US16674088

    申请日:2019-11-05

    Abstract: Provided is a user equipment (UE) including a storage, and a controller that may identify a first assembly file, among a plurality of assembly files of a first application, having a first usage frequency that is equal to or greater than a predetermined threshold, ahead-of-time (AOT) compile the first assembly file based on the first assembly file having the first usage frequency that is equal to or greater than the predetermined threshold, obtain a first compilation result based on AOT compiling the first assembly file, store the first compilation result in the storage, and execute the first application by using the first compilation result stored in the storage based on a request to execute the first application.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开

    公开(公告)号:US20240064964A1

    公开(公告)日:2024-02-22

    申请号:US18191291

    申请日:2023-03-28

    CPC classification number: H10B12/315 H10B12/485 H10B12/482 H10B12/488

    Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate including an active region defined by a device isolation layer, a bit line which is disposed on the substrate and extends in a first direction, a bit line contact which is disposed between the bit line and the substrate and connects the bit line to the active region, a bit line spacer which extends along a sidewall of the bit line, and a bit line contact spacer which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line.

    PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME

    公开(公告)号:US20210233574A1

    公开(公告)日:2021-07-29

    申请号:US17227412

    申请日:2021-04-12

    Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

    DEVICE FOR REDUCING STANDBY POWER AND ELECTRONIC DEVICE THEREFOR

    公开(公告)号:US20210173470A1

    公开(公告)日:2021-06-10

    申请号:US16763758

    申请日:2018-11-14

    Inventor: Jong Min KIM

    Abstract: Disclosed are a device and a method for reducing standby power consumption in an electronic device. An electronic device includes a power supply device for supplying power for driving the electronic device; and a system device driven on the basis of the power supplied from the power supply device, wherein the power supply device can include a AC-DC converter for converting alternating current power received from an external power device into direct current power; and a connection circuit for selectively connecting the external power device and the direct current converter on the basis of an operation mode of the electronic device. Other embodiments can be possible.

    MEMORY MANAGEMENT SYSTEM AND METHOD FOR MANAGING MEMORY

    公开(公告)号:US20230141225A1

    公开(公告)日:2023-05-11

    申请号:US17864088

    申请日:2022-07-13

    CPC classification number: G06F9/45558 G06F9/4881 G06F2009/45583

    Abstract: A memory management system includes a first virtual machine, a second virtual machine, and a hypervisor configured to manage a region to which the first virtual machine and the second virtual machine access in a memory, control the first virtual machine to access a first region and a shared region in the memory, control the second virtual machine to access the shared region and a second region different from the first region in the memory, and in response to a request of the first virtual machine, store an in-memory data isolation (IMDI) table that indicates an IMDI region that a task of the first virtual machine accesses and a task of the second virtual machine does not access, in the memory.

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