公开(公告)号：US20240015948A1

公开(公告)日：2024-01-11

申请号：US18333084

申请日：2023-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG ,  Jongyeong MIN ,  Jiye BAEK ,  Yeseul LEE ,  Jinwook LEE ,  Changhwa JUNG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/34

Abstract: A method of manufacturing an integrated circuit device may include forming a plurality of lower electrodes above a substrate, forming a supporter configured to support the plurality of lower electrodes, forming a dielectric film on the plurality of lower electrodes and the supporter, and forming an upper electrode on the dielectric film. The dielectric film may include a lower leakage current prevention layer on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter, a first capacitor material layer on the lower leakage current prevention layer, an upper material layer on the first capacitor material layer, and a second capacitor material layer on the upper material layer.

公开(公告)号：US20240015949A1

公开(公告)日：2024-01-11

申请号：US18333213

申请日：2023-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG ,  Jongyeong MIN ,  Jiye BAEK ,  Yeseul LEE ,  Jinwook LEE ,  Wonsik CHOI

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/34

Abstract: An integrated circuit device may include a plurality of lower electrodes above a substrate, a supporter between the plurality of lower electrodes, an upper electrode on the plurality of lower electrodes, and a capacitor dielectric film between the upper electrode and the plurality of lower electrodes. The supporter may include one of a metal oxide, a metal nitride, and a metal oxynitride. A portion of the capacitor dielectric film may include a dopant. The dopant in the portion of the capacitor dielectric film and a metal in the supporter may be a same metal.

公开(公告)号：US20250081483A1

公开(公告)日：2025-03-06

申请号：US18636601

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeseul LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Jinwook LEE

IPC: H10B12/00

Abstract: An integrated circuit device includes a lower electrode, a dielectric film covering the lower electrode, an upper electrode covering the dielectric film, and a multilayered interface structure between the dielectric film and the upper electrode, wherein the multilayered interface structure includes a transition metal-aluminum (Al) complex oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al complex oxide layer being in contact with the dielectric film, and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al complex oxide layer.

公开(公告)号：US20250081431A1

公开(公告)日：2025-03-06

申请号：US18809483

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Yeseul LEE

IPC: H10B12/00

Abstract: An integrated circuit device comprising; a transistor on a substrate, and a capacitor structure electrically connected to the transistor. The capacitor structure includes a lower electrode, a lower interface film on the lower electrode, a capacitor dielectric film on the lower interface film, an upper interface film on the capacitor dielectric film, and an upper electrode on the upper interface film. The lower interface film includes a first lower interface layer including metal oxide doped with an impurity, a second lower interface layer including a material that is substantially the same as a material of the first lower interface layer and doped with nitrogen, and a third lower interface layer including a material that is identical to a material of the capacitor dielectric film and doped with nitrogen, the first to third lower interface layers being sequentially stacked on the lower electrode, and wherein the upper interface film includes a first upper interface layer including metal oxide, a second upper interface layer including a material that is identical to a material of the first upper interface layer and doped with nitrogen, and a third upper interface layer including a material that is identical to the material of the capacitor dielectric film and doped with nitrogen, the first to third upper interface layers being sequentially stacked on the upper electrode.

公开(公告)号：US20240038829A1

公开(公告)日：2024-02-01

申请号：US18295433

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiye BAEK ,  Yi Rang Lim

IPC: H01L21/3213 ,  H01L21/285

CPC classification number: H01L28/60 ,  H01L21/32135 ,  H01L21/28556

Abstract: A method for fabricating a semiconductor device includes sequentially stacking a sacrificial layer and a support layer on a substrate, forming bottom electrodes penetrating the sacrificial layer and the support layer to come into contact with the substrate, patterning the support layer to form a support pattern that connects the bottom electrodes to each other, removing the sacrificial layer to expose surfaces of the bottom electrodes, depositing a conductive layer on the exposed surfaces of the bottom electrodes and a surface of the support pattern, and etching the conductive layer. The etching the conductive layer includes selectively removing the conductive layer on the support pattern to expose the surface of the support pattern. The depositing the conductive layer and the etching the conductive layer are alternately performed in a same chamber.

公开(公告)号：US20230163162A1

公开(公告)日：2023-05-25

申请号：US17941688

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak JEON ,  Jiye BAEK ,  Hanjin LIM

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

Abstract: A semiconductor device of the disclosure may include a substrate, a gate structure on the substrate, a capacitor contact structure connected to the substrate, a lower electrode connected to the capacitor contact structure, a supporter supporting a sidewall of the lower electrode, an interfacial layer covering the lower electrode and including a halogen material, a capacitor insulating layer covering the interfacial layer and the supporter, and an upper electrode covering the capacitor insulating layer. The interfacial layer may include a first surface contacting the lower electrode, and a second surface contacting the capacitor insulating layer. The halogen material of the interfacial layer may be closer to the first surface than to the second surface.