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公开(公告)号:US20240221843A1
公开(公告)日:2024-07-04
申请号:US18470931
申请日:2023-09-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minji CHO , Jisang LEE , Sehwan PARK , Jinyoung KIM , Joonsuc JANG
CPC classification number: G11C16/26 , G11C16/0433 , G11C16/08
Abstract: Disclosed is a method of operating a memory device including a memory cell array. The memory cell array includes a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells. The method includes performing an additional read operation on the plurality of memory cells by adjusting a voltage level applied to a selected word line WLN connected to memory cells to be additionally read for improvements in memory cell sensing characteristics and a voltage level applied to a plurality of unselected word lines WLUnselect, and performing a main read operation on the plurality of memory cells by adjusting a voltage level applied to at least one first word line among the plurality of unselected word lines WLUnselect to be different from a voltage level applied to the at least one first word line in the additional read operation.
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2.
公开(公告)号:US20220013184A1
公开(公告)日:2022-01-13
申请号:US17336910
申请日:2021-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Garam KIM , Hyunggon KIM , Jisang LEE , Joonsuc JANG , Wontaeck JUNG
Abstract: A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.
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