公开(公告)号：US20210242870A1

公开(公告)日：2021-08-05

申请号：US17021728

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Youngmin JO ,  Jungjune PARK ,  Jindo BYUN ,  Dongho SHIN ,  Jeongdon IHM

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/08 ,  G11C7/10 ,  G11C8/10

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US20230402076A1

公开(公告)日：2023-12-14

申请号：US18455904

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/173 ,  G11C8/18 ,  G11C29/42

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1063 ,  H03K19/1737 ,  G11C8/18 ,  G11C29/42 ,  G11C7/1084

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US20210408970A1

公开(公告)日：2021-12-30

申请号：US17227996

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan HONG ,  Youngsoo SOHN ,  Jeongdon IHM ,  Changhyun BAE ,  Yoochang SUNG

IPC: H03F1/26 ,  H03F3/19

Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

公开(公告)号：US20210134336A1

公开(公告)日：2021-05-06

申请号：US17150307

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon NA ,  Jeongdon IHM ,  Jangwoo LEE ,  Byunghoon JEONG

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

公开(公告)号：US20210065803A1

公开(公告)日：2021-03-04

申请号：US16834025

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: G11C16/06 ,  H01L25/065 ,  H01L23/66 ,  H01L25/18

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US20240329886A1

公开(公告)日：2024-10-03

申请号：US18738172

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon NA ,  Jeongdon IHM ,  Jangwoo LEE ,  Byunghoon JEONG

IPC: G06F3/06 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/0483

Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

公开(公告)号：US20220368328A1

公开(公告)日：2022-11-17

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jinhyeok BAEK ,  Yoochang SUNG ,  Changsik YOO ,  Jeongdon IHM

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US20210383848A1

公开(公告)日：2021-12-09

申请号：US17411421

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42 ,  H03K19/173

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US20210359684A1

公开(公告)日：2021-11-18

申请号：US17389148

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Youngmin JO ,  Jungjune PARK ,  Jindo BYUN ,  Dongho SHIN ,  Jeongdon IHM

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US20210366546A1

公开(公告)日：2021-11-25

申请号：US17393784

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: G11C16/06 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.