公开(公告)号：US20210408970A1

公开(公告)日：2021-12-30

申请号：US17227996

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan HONG ,  Youngsoo SOHN ,  Jeongdon IHM ,  Changhyun BAE ,  Yoochang SUNG

IPC: H03F1/26 ,  H03F3/19

Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

公开(公告)号：US20140333346A1

公开(公告)日：2014-11-13

申请号：US14272975

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan BAE ,  Kee-won KWON ,  Kyoungho KIM ,  Jung Hoon CHUN ,  Youngsoo SOHN ,  Seok KIM

IPC: H03L7/087

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。

公开(公告)号：US20160315625A1

公开(公告)日：2016-10-27

申请号：US15179202

申请日：2016-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan BAE ,  Kee-Won KWON ,  Kyungho KIM ,  Jung Hoon CHUN ,  Youngsoo SOHN ,  Seok KIM

IPC: H03L7/089 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。