公开(公告)号：US12002731B2

公开(公告)日：2024-06-04

申请号：US17387212

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  In Hyo Hwang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3735 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: Provided is a semiconductor package including a stiffener. The semiconductor package comprises a circuit board, a semiconductor chip on the circuit board, and a stiffener around the semiconductor chip, wherein the stiffener includes a first metal layer, a core layer, and a second metal layer sequentially stacked.

公开(公告)号：US20240079336A1

公开(公告)日：2024-03-07

申请号：US18236190

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun CHUNG ,  Young Lyong Kim ,  In Hyo Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253

Abstract: Provided is a semiconductor package. The semiconductor package includes a redistribution line structure comprising a plurality of redistribution line patterns; a first semiconductor chip and a second semiconductor chip on the redistribution line structure and spaced apart from each other; a bridge structure between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and comprising a plurality of connection wiring patterns configured to electrically connect the first semiconductor chip to the second semiconductor chip; and a molding layer surrounding a sidewall of the bridge structure and filled between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and between the first semiconductor chip and the second semiconductor chip, wherein lowermost surfaces of the plurality of connection wiring patterns are above uppermost surfaces of the plurality of redistribution line patterns.