公开(公告)号：US20200265908A1

公开(公告)日：2020-08-20

申请号：US16865675

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  Il Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C27/00 ,  G11C16/28 ,  G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G06F11/10

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20200286545A1

公开(公告)日：2020-09-10

申请号：US16677930

申请日：2019-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jun YOON

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/56 ,  G11C7/06

Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.

公开(公告)号：US20190287629A1

公开(公告)日：2019-09-19

申请号：US16154111

申请日：2018-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  II Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C16/28 ,  G11C11/56 ,  G06F11/10 ,  G06F3/06

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.