Abstract:
An image sensor including: a pixel array including first and second pixels connected to a column line; a row driver to provide the first pixel with a first selection signal based on a clamp voltage, and to provide the second pixel with a second selection signal based on a selection voltage, wherein the first pixel outputs a first output voltage in response to the first selection signal, and the second pixel outputs a second output voltage in response to the second selection signal, wherein the first and second output voltages are output as a pixel signal through the column line, wherein a voltage of the pixel signal corresponds to a voltage obtained by clamping the second output voltage with the first output voltage, and wherein a change in a voltage level of the first output voltage due to a temperature is compensated for b the clamp voltage.
Abstract:
An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.
Abstract:
An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.
Abstract:
An image sensor includes a unit pixel, a first compensation circuit generating a first compensation voltage signal to compensate for horizontal noise corresponding to a variation in an input signal of a horizontal line coupled to the column line, a second compensation circuit generating a second compensation voltage signal to compensate for power noise corresponding to a variation in a power supply voltage, and a readout circuit including a first transistor, having a gate connected to an output terminal of the first compensation circuit, and a second transistor, connected to the first transistor in parallel, having a gate connected to an output terminal of the second compensation circuit, the readout circuit being configured to calibrate at least one of an output signal of the unit pixel and a ramp voltage signal, output by a ramp generator, using the first compensation voltage signal and the second compensation voltage signal.
Abstract:
An image sensor includes a unit pixel, a first compensation circuit generating a first compensation voltage signal to compensate for horizontal noise corresponding to a variation in an input signal of a horizontal line coupled to the column line, a second compensation circuit generating a second compensation voltage signal to compensate for power noise corresponding to a variation in a power supply voltage, and a readout circuit including a first transistor, having a gate connected to an output terminal of the first compensation circuit, and a second transistor, connected to the first transistor in parallel, having a gate connected to an output terminal of the second compensation circuit, the readout circuit being configured to calibrate at least one of an output signal of the unit pixel and a ramp voltage signal, output by a ramp generator, using the first compensation voltage signal and the second compensation voltage signal.
Abstract:
A CDS circuit includes first capacitors; second capacitors; and a switch arrangement which, in response to a switch control signal, connects the first capacitors in series between a pixel signal output node and a ground to compress the pixel signal and connects the second capacitors in series between a ramp signal output node and the ground to compress the ramp signal, or connects the first capacitors in parallel between the pixel signal output node and a first input node of the comparator and connects the second capacitors in parallel between the ramp signal output node and a second input node of the comparator.