公开(公告)号：US20240030119A1

公开(公告)日：2024-01-25

申请号：US18374396

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49833 ,  H01L25/0657 ,  H01L23/49894 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20230420402A1

公开(公告)日：2023-12-28

申请号：US18244462

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  DONGKYU KIM ,  JUNG-HO PARK ,  YEONHO JANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L23/3128 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/023 ,  H01L2224/0401

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US20240136311A1

公开(公告)日：2024-04-25

申请号：US18234529

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.

公开(公告)号：US20230207441A1

公开(公告)日：2023-06-29

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM ,  EUNGKYU KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L24/17 ,  H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L25/18

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20240072006A1

公开(公告)日：2024-02-29

申请号：US18326554

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： WON IL LEE ,  HYUNGCHUL SHIN ,  GWANGJAE JEON ,  ENBIN JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip including a first main region and a first edge region, and a second semiconductor chip on the first semiconductor chip and including a second main region and a second edge region. The first semiconductor chip includes a first main pad and a first dummy pad respectively on the first main region and the first edge region on a top surface of the first semiconductor chip. The second semiconductor chip includes a first semiconductor substrate, a wiring layer below the first semiconductor substrate and including a wiring dielectric layer and wiring patterns, a second main pad and a second dummy pad respectively on the second main region and the second edge region below the wiring layer. A thickness of the wiring layer is greater on the second main region than on the second edge region.

公开(公告)号：US20210398890A1

公开(公告)日：2021-12-23

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20220084924A1

公开(公告)日：2022-03-17

申请号：US17222912

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNGKYU KIM ,  JONGYOUN KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.

公开(公告)号：US20220059444A1

公开(公告)日：2022-02-24

申请号：US17206291

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM ,  EUNGKYU KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20210118788A1

公开(公告)日：2021-04-22

申请号：US16885546

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHYUN LEE ,  GWANGJAE JEON

IPC: H01L23/498

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US20240234349A9

公开(公告)日：2024-07-11

申请号：US18234529

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.