公开(公告)号：US20250089314A1

公开(公告)日：2025-03-13

申请号：US18588089

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon HWANG ,  Hyojin KIM ,  Byungho MOON ,  Myungil KANG ,  Doyoung CHOI

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, including a first active region on a substrate, including a lower channel pattern and lower source/drain patterns connected to the lower channel pattern, the lower channel pattern including a plurality of lower semiconductor patterns stacked and spaced apart from each other in a first direction that is perpendicular to an upper surface of the substrate, and the lower semiconductor patterns including a lowermost first semiconductor pattern, a second active region stacked on the first active region, including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a lower gate electrode on the lower channel pattern, and a lower insulating pattern under the first semiconductor pattern, the first semiconductor pattern spaced apart from the lower insulating pattern in the first direction. The lower gate electrode includes a first portion adjacent to a first sidewall of the lower insulating pattern and extending in the first direction from an upper surface to a bottom surface of the lower gate electrode, a second portion adjacent to a second sidewall of the lower insulating pattern and extending in the first direction from the upper surface to the bottom surface of the lower gate electrode, the second sidewall facing the first sidewall in a second direction which is perpendicular to the first direction, and a third portion in contact with a bottom surface of the lower insulating pattern and extending from the first portion to the second portion in the second direction.

公开(公告)号：US20170345679A1

公开(公告)日：2017-11-30

申请号：US15602599

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong KWON ,  Sangjin KIM ,  Donghoon HWANG ,  Sebeom OH ,  Yunkyeong JANG

IPC: H01L21/56 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/544

CPC classification number: H01L21/565 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823468 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a lower mold layer on a substrate that includes first and second regions, forming first and second intermediate mold patterns on the first and second regions, respectively, forming first spacers on sidewalls of the first and second intermediate mold patterns, etching the lower mold layer to form first and second lower mold patterns on the first and second regions, respectively, and etching the substrate to form active patterns and dummy patterns on the first and second regions, respectively. A first distance between a pair of the first intermediate mold patterns may be greater than a second distance between a pair of the second intermediate mold patterns, and the second lower mold patterns may include at least one first merged pattern, whose width is substantially equal to the second distance.

公开(公告)号：US20250107180A1

公开(公告)日：2025-03-27

申请号：US18755008

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee CHO ,  Byungho MOON ,  Donghoon HWANG

IPC: H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device including a base substrate layer, a sheet separation wall extending on the base substrate layer in a first horizontal direction, a pair of nanosheet stacked structures including the sheet separation wall therebetween and apart from each other in a second horizontal direction, the second horizontal direction different from the first horizontal direction, the pair of nanosheet stacked structures each including a plurality of nanosheets, a plurality of cladding patterns between a first end of each of the plurality of nanosheets included in each of the pair of nanosheet stacked structures and the sheet separation wall, and a pair of gate electrodes extending on the pair of nanosheet stacked structures in the second horizontal direction.

公开(公告)号：US20240258328A1

公开(公告)日：2024-08-01

申请号：US18416473

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon HWANG ,  Inchan Hwang ,  Hyojin Kim

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1266

Abstract: An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

公开(公告)号：US20250126861A1

公开(公告)日：2025-04-17

申请号：US18745312

申请日：2024-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok PARK ,  Donghoon HWANG ,  Myungil KANG ,  Wookhwan SONG ,  Doyoung CHOI

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate; an active region extending in a first direction on the substrate; a gate structure extending in a second direction on the active region and intersecting the active region; a source/drain region on the active region on a side of the gate structure; a separation pattern extending in the first direction and separating the gate structure; and a contact structure on the separation pattern and crossing the separation pattern, the contact structure being electrically connected to the source/drain region, wherein the contact structure includes a first portion and a second portion, the first portion contacts the separation pattern, the second portion contacts the source/drain region, a lower surface of the second portion is at a level lower than a lower surface of the first portion, and a lowermost end of the contact structure is spaced apart from the separation pattern.

公开(公告)号：US20250072066A1

公开(公告)日：2025-02-27

申请号：US18412812

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooseok PARK ,  Wookhwan SONG ,  Donghoon HWANG ,  Myungil KANG ,  Taehyun RYU ,  Namhyun LEE

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a first active pattern, a second active pattern spaced apart at a first distance from the first active pattern, a third active pattern spaced apart at a second distance from the second active pattern, a first device isolation layer between the first and second active patterns, a second device isolation layer between the second and third active patterns, a first channel structure overlapping the first active pattern, a second channel structure overlapping the second active pattern, a third channel structure overlapping the third active pattern, and a separation dielectric layer between the first and second channel structures. The separation dielectric layer may overlap the first device isolation layer. A level of a top surface of the first device isolation layer may be higher than a level of a top surface of the second device isolation layer.

公开(公告)号：US20250031412A1

公开(公告)日：2025-01-23

申请号：US18677236

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin KIM ,  Donghoon HWANG ,  Myungil KANG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes gate structures on an insulation structure, the gate structures disposed in a second direction substantially parallel to an upper surface of the insulation structure, source/drain layers at opposite sides, respectively, of each gate structure in a first direction intersecting the second direction, semiconductor patterns disposed in a third direction substantially perpendicular to the upper surface of the insulation structure, the semiconductor patterns extending through each of the gate structures and contacting the source/drain layers, a first division pattern between the gate structures, and a connection pattern extending into and contacting an upper portion of the first division pattern and upper portions of the gate structures adjacent to the first division pattern, a lower surface of the connection pattern being lower than upper surfaces of the gate structures and an upper surface of the connection pattern being higher than the upper surfaces of the gate structures.

公开(公告)号：US20240258437A1

公开(公告)日：2024-08-01

申请号：US18510146

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Donghoon HWANG ,  Inchan HWANG ,  Hyojin KIM ,  Jaehyoung LIM

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line, a first FET on the back-side wiring layer, a second FET over the first FET, a front-side wiring layer over the second FET, a first through-electrode connecting the first FET to the second FET, and a second through-electrode connecting the front-side and back-side power lines. The front-side wiring layer may extend in a first direction and may include a front-side power line connected to the second back-side power line. The first FET and the second FET may share a gate extending in a second direction. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.