公开(公告)号：US11921158B2

公开(公告)日：2024-03-05

申请号：US18075542

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Sung Kim ,  Yun-Hyok Choi ,  Gyuyeol Kim ,  Sungjung Kim ,  Cheol-Heui Park ,  Sanghoon Lee ,  Jae-Woong Choi

IPC: G01R31/3177 ,  G01R1/073 ,  G01R23/165 ,  G01R25/04 ,  G01R31/317 ,  G01R31/3183 ,  G04F10/00

CPC classification number: G01R31/3177 ,  G01R1/07314 ,  G01R23/165 ,  G01R25/04 ,  G01R31/31713 ,  G01R31/31715 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318328 ,  G04F10/005

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

公开(公告)号：US09064546B2

公开(公告)日：2015-06-23

申请号：US14069188

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Chul-Woo Park ,  Cheol-Heui Park

IPC: G11C8/10 ,  G11C8/06 ,  G11C7/12 ,  G11C29/18 ,  G11C16/24 ,  G11C29/12

CPC classification number: G11C8/06 ,  G11C7/12 ,  G11C8/10 ,  G11C16/24 ,  G11C29/18 ,  G11C2029/1204 ,  G11C2029/1806

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract translation: 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。