公开(公告)号：US20240313066A1

公开(公告)日：2024-09-19

申请号：US18409031

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo Kyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: H01L29/40 ,  G03F7/00 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/401 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  G03F7/2004 ,  G03F7/2022 ,  G03F7/7045

Abstract: A method of fabricating a semiconductor device may include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit line structure on the cell region, forming a preliminary conductive layer to cover the bit line structure and the peripheral gate structure, and etching the preliminary conductive layer to form a landing pad and peripheral conductive pads. The etching of the preliminary conductive layer may include forming lower and photoresist layers on the preliminary conductive layer, performing a first exposure process on the photoresist layer, performing a second exposure process on the photoresist layer, and etching the preliminary conductive layer using the photoresist and lower layers as an etch mask. The first exposure process may expose a portion of the photoresist layer that is on the cell region to light.

公开(公告)号：US20240160115A1

公开(公告)日：2024-05-16

申请号：US18347129

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyong JUNG ,  Dohun KIM ,  Joonhyun KIM ,  Jeongjin LEE ,  Seungyoon LEE ,  Chan HWANG

IPC: G03F7/00 ,  H01L21/027

CPC classification number: G03F7/70633 ,  G03F7/706839 ,  H01L21/027

Abstract: Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.

公开(公告)号：US20240152064A1

公开(公告)日：2024-05-09

申请号：US18372296

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mincheol KWAK ,  Jeongjin LEE ,  Seungyoon LEE ,  Chan HWANG

IPC: G03F9/00 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F9/7073 ,  G03F7/70141 ,  H01L21/027 ,  H01L21/31144

Abstract: A photolithography system includes a light source, a photomask stage, a projection optical system and a wafer stage, and the projection optical system includes an anamorphic lens. In a photolithography method, a wafer and a photomask are mounted on the wafer stage and the photomask stage, respectively, and a first exposure process is performed using the photomask to transfer layouts of patterns included in the photomask to a first half field of the wafer. A relative position of the photomask with respect to the wafer is changed, and a second exposure process is performed to transfer the layouts of the patterns included in the photomask to a second half field of the wafer.

公开(公告)号：US20150294455A1

公开(公告)日：2015-10-15

申请号：US14581232

申请日：2014-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Jin LEE ,  Seung-Hwa OH ,  Chan HWANG

IPC: G06T7/00 ,  G06T1/00 ,  G06K9/46 ,  H01L23/544 ,  G01N21/88

CPC classification number: G06K9/46 ,  G01N21/9501 ,  G01N21/95607 ,  G01N2021/8854 ,  G01N2021/8877 ,  G01N2021/8887 ,  G03F7/7065 ,  G06T7/0006 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of testing pattern reliability and methods of testing a semiconductor device using the same. A method of testing pattern reliability may include acquiring an optical image of a wafer on which a plurality of patterns are formed, evaluating degrees of damage of ones of the plurality of patterns based on the optical image, determining a respective reliability of the ones of the plurality of patterns according to the evaluated respective degrees of damage, and mapping the reliability of the ones of the plurality of patterns based on locations of the respective patterns on the wafer.

Abstract translation: 提供了测试图案可靠性的方法以及使用其测试半导体器件的方法。 测试图案可靠性的方法可以包括获取其上形成有多个图案的晶片的光学图像，基于光学图像评估多个图案中的一个的损伤程度，确定其中的一个的可靠性 根据评估的相应损伤程度的多个图案，并且基于晶片上的各个图案的位置来映射多个图案中的图案的可靠性。

公开(公告)号：US20240152043A1

公开(公告)日：2024-05-09

申请号：US18381731

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minseung SONG ,  Janghoon KIM ,  Sangho YUN ,  Chan HWANG

IPC: G03F1/22 ,  G03F1/70 ,  G03F1/80 ,  G03F7/00

CPC classification number: G03F1/22 ,  G03F1/70 ,  G03F1/80 ,  G03F7/70616

Abstract: A method of manufacturing an extreme ultraviolet mask including preparing a preliminary layout, forming a plurality of preliminary target patterns by using a plurality of preliminary spacer patterns formed by using the preliminary layout, evaluating presence or absence of an abnormal target pattern among the plurality of preliminary target patterns, preparing a layout configured to form a plurality of spacer patterns by modifying the preliminary layout when the plurality of preliminary target patterns include the abnormal target pattern, and manufacturing an extreme ultraviolet mask with the layout to form a plurality of target patterns by using the plurality of spacer patterns, wherein, the plurality of preliminary spacer patterns extend in one direction.

公开(公告)号：US20220066328A1

公开(公告)日：2022-03-03

申请号：US17234908

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon Hwan CHA ,  Chan HWANG ,  Woo Jin JUNG

IPC: G03F7/20

Abstract: A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area. The controller generates a second mask pattern based on the first mask pattern and the first semiconductor substrate image, and provides the second mask pattern to the photolithography apparatus.

公开(公告)号：US20200152638A1

公开(公告)日：2020-05-14

申请号：US16745956

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon-mok HA ,  Jae-hee KIM ,  Chan HWANG ,  Jong-hyuk KIM

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.

公开(公告)号：US20170261317A1

公开(公告)日：2017-09-14

申请号：US15448325

申请日：2017-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon LEE ,  Chan HWANG ,  Jeong Jin LEE

IPC: G01B11/27 ,  G01B11/00

CPC classification number: G01B11/272 ,  G01B11/002 ,  G03F9/7084 ,  H01L2224/16145

Abstract: A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.

公开(公告)号：US20240222201A1

公开(公告)日：2024-07-04

申请号：US18454219

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inbeom YIM ,  Jeongjin LEE ,  Seungyoon LEE ,  Chan HWANG

IPC: H01L21/66 ,  G03F1/70 ,  H01L21/027 ,  H01L21/3213

CPC classification number: H01L22/20 ,  G03F1/70 ,  H01L21/0274 ,  H01L21/32139

Abstract: The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

公开(公告)号：US20240213023A1

公开(公告)日：2024-06-27

申请号：US18373455

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doo Gyu LEE ,  Jeong Jin LEE ,  Min-Cheol KWAK ,  Seung Yoon LEE ,  Chan HWANG

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  H01L21/32139 ,  H01L22/12

Abstract: A method for fabricating a semiconductor device using an overlay measurement and a semiconductor device fabricated by the method are provided. The method includes forming a lower pattern including a lower overlay key pattern having a first pitch, on a substrate, forming an upper pattern including an upper overlay key pattern having a second pitch different from the first pitch, on the lower pattern, measuring an overlay between the lower overlay key pattern and the upper overlay key pattern, removing the upper overlay key pattern, and after removing the upper overlay key pattern, performing an etching process using the upper pattern as an etching mask.