公开(公告)号：US20250070022A1

公开(公告)日：2025-02-27

申请号：US18634325

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun LEE ,  Hyejin KIM ,  Yonghyeok SON ,  Jichang SIM ,  Joo-Sung LEE ,  Yujin CHO

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell array region, a core region, and a peripheral circuit region, a core circuit wiring on the core region of the substrate, a core signal wiring overlapping the core circuit wiring, and a contact plug between the core circuit wiring and the core signal wiring. The contact plug may connect the core circuit wiring to the core signal wiring. A positional relationship between the core signal wiring and the contact plug may be different depending on distance from the peripheral circuit region.

公开(公告)号：US20240280895A1

公开(公告)日：2024-08-22

申请号：US18381773

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam YEEM ,  Hoin LEE ,  Dongkyun LEE ,  Sangchul YANG ,  Byung-Hyun LEE

IPC: G03F1/70 ,  H01L21/027

CPC classification number: G03F1/70 ,  H01L21/027 ,  H10B12/315

Abstract: A method of fabricating a semiconductor device may include forming a target pattern on a first wafer by performing a first exposure process, measuring a misalignment value of the target pattern, calculating a block misalignment value and a pattern misalignment value based on the misalignment value, calculating a block correction value based on the block misalignment value and calculating a pattern correction value based on the pattern misalignment value, and performing a second exposure process on a second wafer, based on the block correction value and the pattern correction value.

公开(公告)号：US20230005917A1

公开(公告)日：2023-01-05

申请号：US17901210

申请日：2022-09-01

Applicant: Samsung Electronics Co., LTD.

Inventor： Cheonbae KIM ,  Seungjin KIM ,  Dongkyun LEE

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

公开(公告)号：US20210296431A1

公开(公告)日：2021-09-23

申请号：US17036731

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung CHOI ,  SangJae PARK ,  Dongkyun LEE

IPC: H01L49/02

Abstract: An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.