Abstract:
A method of driving a display panel includes providing a switching element of a pixel of the display panel with a first polarity gate signal through a gate line connected to the switching element when the switching element receives a first polarity data signal having a first polarity with respect to a reference signal, and providing the switching element with a second polarity gate signal through the gate line when the switching element receives a second polarity data signal having a second polarity with respect to the reference signal through the data line.
Abstract:
A display panel includes a high pixel electrode including a first stem which extends substantially in a first direction, and a second stem which extends substantially in a second direction crossing the first direction, a low pixel electrode including a first stem which extends substantially in the first direction, and a second stem which extends substantially in the second direction, a data line which extends in the second direction, a high storage line which extends substantially in the second direction and overlaps the second stem of the high pixel electrode, and a low storage line which extends substantially in the second direction and overlaps the second stem of the low pixel electrode.
Abstract:
A display panel includes a gate line, a gate electrode, a planarization layer, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode, and a pixel electrode. The gate electrode extends from the gate line. The planarization layer covers the gate line and the gate electrode to have an opening exposing a portion of the gate electrode formed therethrough. The gate insulation layer covers a portion of the gate electrode exposed by the opening and the planarization layer. The active layer is formed on the gate insulation layer and corresponds to the gate electrode. The data line is formed. The source electrode extends from the data line to cover a portion of the opening. The drain electrode is spaced apart from the source electrode and covers a portion of the opening. The pixel electrode is connected to the drain electrode.
Abstract:
A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.
Abstract:
A thin film transistor array panel includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and intersecting the gate line, a thin film transistor connected to the gate line and the data line, an insulating layer on the gate line, the data line, and the thin film transistor, a first auxiliary line on the insulating layer and connected to the gate line, a second auxiliary line on the insulating layer and connected to the data line, and a pixel electrode connected to the thin film transistor.
Abstract:
A display apparatus includes a display panel, a gate driving part, and a date driving part. The display panel includes a switching element disposed in association with a pixel, a main gate line connected to the switching element, and a sub gate line spaced apart from the main gate line and connected to the main gate line via a first connecting part. The gate driving part is configured to: provide the main gate line with a main gate signal, and provide the sub gate line with a sub gate signal. The sub gate signal includes a transmission difference from the main gate signal. The data driving part is configured to provide a data line with a data signal.
Abstract:
A display panel includes a high pixel electrode including a first stem which extends substantially in a first direction, and a second stem which extends substantially in a second direction crossing the first direction, a low pixel electrode including a first stem which extends substantially in the first direction, and a second stem which extends substantially in the second direction, a data line which extends in the second direction, a high storage line which extends substantially in the second direction and overlaps the second stem of the high pixel electrode, and a low storage line which extends substantially in the second direction and overlaps the second stem of the low pixel electrode.
Abstract:
A gate drive circuit includes a shift register having a plurality of stages, in which an n-th stage (‘n’ is a natural number) of the plurality of stages is connected to at least one subsequent stage. The n-th stage includes a pull-up part configured to output a high voltage of an n-th gate signal using a high voltage of a clock signal as in response to a high voltage of a control node, a control pull-down part configured to pull-down a voltage of the control node into a low voltage in response to a carry signal outputted from at least one of next stages of the n-th stage and receiving a back-bias voltage corresponding to the low voltage, and a carry part configured to output the high voltage of the clock signal as an n-th carry signal in response to a high voltage of the control node.
Abstract:
A display panel includes a gate line which extends substantially in a first direction, a first data line which extends substantially in a second direction substantially perpendicular to the first direction, a second data line spaced apart from the first data line in the first direction and which extends substantially in the second direction, a high pixel electrode disposed between the first data line and the second data line and disposed adjacent to the gate line, a low pixel electrode disposed between the first data line and the second data line and disposed opposite to the high pixel electrode with reference to the gate line, a high storage line which extends substantially in the second direction and overlaps the high pixel electrode, and a low storage line which extends substantially in the second direction and overlaps the low pixel electrode.
Abstract:
A display panel includes a gate line, a first data line crossing the gate line, a first voltage applied to the first data line, a second data line in parallel with the first data line and spaced apart from the first data line, a second voltage different from the first voltage applied to the second data line, a first thin film transistor electrically connected to the first data line, a second thin film transistor electrically connected to the second data line, a first pixel electrode electrically connected to the first thin film transistor, and disposed between the first data line and the second data line, and a second pixel electrode electrically connected to the second thin film transistor, and disposed opposite to the first pixel electrode with reference to the second data line.